Freescale Semiconductor MCF51QE128RM manual Data Result Low Register Adcrl, ADR10 ADR9 ADR8

Analog-to-Digital Converter (S08ADC12V1)

If the MODE bits are changed, any data in ADCRH becomes invalid.

R

W

Reset:

7	6	5	4	3	2	1	0
0	0	0	0	ADR11	ADR10	ADR9	ADR8
0	0	0	0	0	0	0	0

Figure 11-5. Data Result High Register (ADCRH)

11.3.4Data Result Low Register (ADCRL)

ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion. This register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. In 12-bit and 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the intermediate conversion results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE bits are changed, any data in ADCRL becomes invalid.

R

W

Reset:

7	6	5	4	3	2	1	0
ADR7	ADR6	ADR5	ADR4	ADR3	ADR2	ADR1	ADR0
0	0	0	0	0	0	0	0

Figure 11-6. Data Result Low Register (ADCRL)

11.3.5Compare Value High Register (ADCCVH)

In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are compared to the upper four bits of the result following a conversion in 12-bit mode when the compare function is enabled.

R

W

Reset:

7	6	5	4	3	2	1	0
0	0	0	0	ADCV11	ADCV10	ADCV9	ADCV8
0	0	0	0	0	0	0	0

Figure 11-7. Compare Value High Register (ADCCVH)

MCF51QE128 MCU Series Reference Manual, Rev. 3

224 Freescale Semiconductor

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