MCF51QE64 MCF51QE32
Page
MCF51QE128 Series Features
Page
MCF51QE128 Reference Manual
MCF51QE128 MCU Series Reference Manual, Rev
Contents
Section Number Title
Freescale Semiconductor
Chapter Resets, Interrupts, and General System Control
Title Chapter Parallel Input/Output Control
127
ColdFire Core
Chapter Interrupt Controller CF1INTC
Analog Comparator 3V ACMPVLPV1
11.1.5
Internal Clock Source S08ICSV3
Chapter Inter-Integrated Circuit S08IICV2
Section Number Title
Real-Time Counter S08RTCV1
Serial Peripheral Interface S08SPIV3
Chapter Timer/Pulse-Width Modulator S08TPMV3
Chapter Version 1 ColdFire Debug CF1DEBUG
Appendix a Revision History
Feature MCF51QE128
MCF51QE128 Series Features by MCU and Package
Chapter Device Overview
Devices in the MCF51QE128/64/32 Series
Xosc
MCU Block Diagram
MCF51QE128/64/32 Block Diagram
System Clocks
V1 ColdFire Core
Internal Clock Source ICS Module
Module Versions
System Clock Distribution
Simplified ICS Block Diagram
Icsirclk
ICS Modes of Operation
FLL Bypassed Internal Low-Power Fbilp
FLL Engaged Internal FEI
FLL Engaged External FEE
Stop Stop
FLL Bypassed External Low-Power Fbelp
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Device Pin Assignment
Chapter Pins and Connections
Pin Lqfp
Pins in bold are added from the next smaller package
Recommended System Connections
Basic System Connections
Reset and Rsto
Power
Oscillator
Background / Mode Select BKGD/MS
General-Purpose I/O and Peripheral Ports
ADC Reference Pins VREFH, Vrefl
Pin
Pin Assignment by Package and Pin Sharing Priority
Priority
Number Port Pin Alt
Port Pin Alt
Number
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Chapter Modes of Operation
Features
Introduction
Overview
MCF51QE128/64/32 Power Modes Conceptual Drawing
SIM BDC PMC
CPU / Power Mode Selections
Stop3
Mode Regulator State
Full On
Run Stop2 LPrun
Transition # From Trigger
Triggers for Transitions Shown in Figure
Secure Mode
Debug Mode
Low-Power Run Mode LPrun
Run Mode
BDM in Low-Power Run Mode
Run Modes
Low-Power Wait Mode LPwait
Wait Mode
BDM in Low-Power Wait Mode
Wait Modes
Stop2 Mode
Stop4 Low Voltage Detect or BDM Enabled in Stop Mode
Stop3 Mode
Low-Range Oscillator Considerations for Stop2
Low-Power Mode Behavior
On-Chip Peripheral Modules in Stop and Low-Power Modes
Abbreviations used in Table
CF1CORE
COP
BDC
ICS
IRQ
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MCF51QE128/64/32 Memory Map
Chapter Memory
MCF51QE128
Kbytes
Register Addresses and Bit Assignments
CPU Access Type Allowed by Region
Read Write Base Address Region Byte
Long Byte
ColdFire Memory Organization
Direct-Page Register Summary Sheet 1
Register Address Name
Direct-Page Register Summary Sheet 2
Direct-Page Register Summary Sheet 3
High-Page Register Summary Sheet 1
Direct-Page Register Summary Sheet 4
High-Page Register Summary Sheet 2
High-Page Register Summary Sheet 3
High-Page Register Summary Sheet 4
High-Page Register Summary Sheet 5
Flash Module Reserved Memory Locations
Reserved Flash Memory Addresses
0x0 0x1 0x2 0x3
0x0000040C
0x0 0x1 0x2 0x3 0x00000408
Reserved Flash Memory Addresses Register
Nvprot
ColdFire Interrupt Controller Memory Map
ColdFire Rapid Gpio Memory Map
V1 ColdFire Rapid Gpio Memory Map
V1 ColdFire Interrupt Controller Memory Map
Flash
RAM
Intcsfrc
Intccfrc
Lov-Voltage Programming Sequence Example
Features
Addresses Desired Value Values Programmed
Flash Clock Divider Register Fcdiv
Register Descriptions
Flash Options Register Fopt and Nvopt
Fcdiv Field Descriptions
10. Fopt Field Descriptions
Flash Configuration Register Fcnfg
11. Fcnfg Field Descriptions
Flash Protection Register Fprot and Nvprot
12. Fprot Field Descriptions
13. Flash Protection Address Range
0x40
0x00-0x3F
0x41 0x00000-0x1EFFF
0x42
Flash Status Register Fstat
Command buffers are full
Fcbef Fccf Fpviol Faccerr Fblank
W1c
Flash Command Register Fcmd
Flash Command Operations
Function Description
15. Fcmd Field Descriptions
200 195 ÷ 200 = 3%
Writing the Fcdiv Register
Commands Impossible
Command Write Sequence
Start
ALL Program and Erase
Erase Verify Command
Flash Commands
16. Flash Command Description
Fcmd NVM
Program Command
11. Example Program Command Flow
Burst Program Command
Command Buffer Empty
Sector Erase Command
Sequential
Programming
13. Example Sector Erase Command Flow
14. Example Mass Erase Command Flow
Mass Erase Command
Illegal Flash Operations
Flash Access Violations
Background Debug Mode
Wait Mode
Operating Modes
Flash Protection Violations
Security
Unsecuring the MCU using Backdoor Key Access
Flash Reset Sequence
Resets
Reset While Flash Command Active
Program and Erase Times
Security
Set PRDIV8 and clock divider fields in CSR3
Sync
Stop
Device is unsecure
Microcontroller Reset
Chapter Resets, Interrupts, and General System Control
Computer Operating Properly COP Watchdog
COP Configuration Options
Control Bits Clock Source COP Overflow Count
Copclks Copt
Illegal Address Reset
Illegal Operation Reset
Pin Configuration Options
Interrupts and Exceptions
Low-Voltage Detect LVD System
Power-On Reset Operation
Edge and Level Sensitivity
External Interrupt Initialization
Peripheral Clock Gating
LVD Reset Operation
LVD Interrupt Operation
Low-Voltage Warning LVW Interrupt Operation
Irqsc Register Field Descriptions
Interrupt Pin Request Status and Control Register Irqsc
Irqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack
Irqpdd
POR
System Reset Status Register SRS
POR LVR
System Options Register 1 SOPT1
SOPT1 Register Field Descriptions
System Options Register 2 SOPT2
SOPT2 Register Field Descriptions
System Device Identification Register SDIDH, Sdidl
SPI1PS SPSCLK1 MOSI1 MISO1 SS1
IIC1PS SDA1 SCL1
Sdidl Register Field Descriptions
Sdidh Register Field Descriptions
Lvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack
LPR Lprs Lpwui Ppde Ppdc Ppdack
SPMSC1 Register Field Descriptions
SPMSC2 Register Field Descriptions
Lvwf Lvdv Lvwv Lvwie
11. LVD and LVW Trip Point Typical Values1
Lvwf
Lvdvlvwv
System Clock Gating Control 2 Register SCGC2
System Clock Gating Control 1 Register SCGC1
12. SCGC1 Register Field Descriptions
TPM3
RTC SPI2 SPI1
13. SCGC2 Register Field Descriptions
FLS
Freescale Semiconductor 109
110 Freescale Semiconductor
Freescale Semiconductor 111
112 Freescale Semiconductor
Port Data and Data Direction
Chapter Parallel Input/Output Control
Freescale Semiconductor 113
Port Slew Rate Enable
Port Internal Pull-up Enable
Pull-up, Slew Rate, and Drive Strength
Data Direction Control Port Data Register Port Read
Port Drive Strength Select
Port Data Set, Clear and Toggle Data Registers
Freescale Semiconductor 115
Keyboard Interrupts
V1 ColdFire Rapid Gpio Functionality
Port Data Set Registers
Port Data Clear Registers
Edge and Level Sensitivity
Edge Only Sensitivity
Pull-up/Pull-down Resistors
Freescale Semiconductor 117
Parallel I/O, Keyboard Interrupt, and Pin Control Registers
Pin Behavior in Stop Modes
Keyboard Interrupt Initialization
Port a Registers
Port a Data Register Ptad
Port a Pull Enable Register Ptape
Port a Data Direction Register Ptadd
PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0
Port a Drive Strength Selection Register Ptads
Port a Slew Rate Enable Register Ptase
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
Port B Data Register Ptbd
Port B Registers
Port B Data Direction Register Ptbdd
Ptads Register Field Descriptions
Port B Slew Rate Enable Register Ptbse
Port B Pull Enable Register Ptbpe
Ptbdd Register Field Descriptions
Ptbpe Register Field Descriptions
Port B Drive Strength Selection Register Ptbds
Port C Registers
Port C Data Register Ptcd
10. Ptbds Register Field Descriptions
Port C Data Set Register Ptcset
Port C Data Direction Register Ptcdd
Port C Data Clear Register Ptcclr
12. Ptcdd Register Field Descriptions
Port C Toggle Register Ptctog
Port C Pull Enable Register Ptcpe
14. Ptcclr Register Field Descriptions
16. Ptcpe Register Field Descriptions
Port D Registers
Port C Slew Rate Enable Register Ptcse
Port C Drive Strength Selection Register Ptcds
Port D Data Register Ptdd
Port D Data Direction Register Ptddd
Port D Pull Enable Register Ptdpe
19. Ptdd Register Field Descriptions
20. Ptddd Register Field Descriptions
Port E Registers
Port D Slew Rate Enable Register Ptdse
Port D Drive Strength Selection Register Ptdds
Port E Data Register Pted
Port E Data Set Register Pteset
Port E Data Direction Register Ptedd
24. Pted Register Field Descriptions
25. Ptedd Register Field Descriptions
Port E Data Clear Register Pteclr
Port E Pull Enable Register Ptepe
Port E Toggle Register Ptetog
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
Port E Drive Strength Selection Register Pteds
Port E Slew Rate Enable Register Ptese
29. Ptepe Register Field Descriptions
30. Ptese Register Field Descriptions
Port F Registers
Port F Pull Enable Register Ptfpe
Port F Data Register Ptfd
Port F Data Direction Register Ptfdd
Port F Drive Strength Selection Register Ptfds
Port F Slew Rate Enable Register Ptfse
34. Ptfpe Register Field Descriptions
35. Ptfse Register Field Descriptions
Port G Data Register Ptgd
Port G Registers
Port G Data Direction Register Ptgdd
36. Ptfds Register Field Descriptions
Port G Slew Rate Enable Register Ptgse
Port G Pull Enable Register Ptgpe
Port G Drive Strength Selection Register Ptgds
39. Ptgpe Register Field Descriptions
Port H Data Register Pthd
Port H Registers
Port H Data Direction Register Pthdd
41. Ptgds Register Field Descriptions
Port H Slew Rate Enable Register Pthse
Port H Pull Enable Register Pthpe
Port H Drive Strength Selection Register Pthds
44. Pthpe Register Field Descriptions
Port J Data Register Ptjd
Port J Registers
Port J Data Direction Register Ptjdd
Port J Slew Rate Enable Register Ptjse
Port J Pull Enable Register Ptjpe
Port J Drive Strength Selection Register Ptjds
49. Ptjpe Register Field Descriptions
10.1 KBI1 Interrupt Status and Control Register KBI1SC
Keyboard Interrupt 1 KBI1 Registers
51. Ptjds Register Field Descriptions
52. KBI1 Pin Mapping
10.2 KBI1 Interrupt Pin Select Register KBI1PE
Keyboard Interrupt 1 KBI2 Registers
10.3 KBI1 Interrupt Edge Select Register KBI1ES
11.2 KBI2 Interrupt Pin Select Register KBI2PE
11.1 KBI2 Interrupt Status and Control Register KBI2SC
57. KBI2SC Register Field Descriptions
58. KBI2PE Register Field Descriptions
59. KBI2ES Register Field Descriptions
11.3 KBI2 Interrupt Edge Select Register KBI2ES
Freescale Semiconductor 143
144 Freescale Semiconductor
Overview
Chapter ColdFire Core
Memory Map/Register Description
Supervisor Access Only Registers
Supervisor/User Access Registers
Data Registers D0-D7
ColdFire Core Programming Model
Supervisor/User Stack Pointers A7 and OTHERA7
Address Registers A0-A6
Data
Freescale Semiconductor 149
Condition Code Register CCR
Vector Base Register VBR
Program Counter PC
CCR Field Descriptions
CPU Configuration Register Cpucr
SR Field Descriptions
Status Register SR
BWD
Instruction Set Architecture Isac
Functional Description
Instruction Enhancements over Revision Isaa
Instruction Description
Exception Processing Overview
Vector Stacked
Exception Vector Assignments
Assignment Numbers Offset Hex Counter
Assignment
Exception Stack Frame Definition
Numbers Offset Hex Counter
SSP →
2.2 S08 and ColdFire Exception Processing Comparison
Fault Status Encodings
Format Field Encodings
FS30 Definition
Attribute S08 V1 ColdFire
Exception Processing Comparison
RTI RTE
Address Error Exception
Access Error Exception
Processor Exceptions
Freescale Semiconductor 159
10. ColdFire Opword Line Definition
Illegal Instruction Exception
Line OpMode Effective Address
OpwordLine Instruction Class
Trace Exception
Privilege Violation
Freescale Semiconductor 161
Unimplemented Line-A Opcode
RTE and Format Error Exception
Unimplemented Line-F Opcode
Debug Interrupt
Trap Instruction Exception
Fault-on-Fault Halt
Unsupported Instruction Exception
Interrupt Exception
Access User read-only BDM read-only
Reset Exception
BDM Load 0x60 D0 Store 0x40 D0
VER REV
11. D0 Hardware Configuration Info Field Description
Flashsz
12. D1 Hardware Configuration Information Field Description
Sramsz
Timing Assumptions
Instruction Execution Timing
13. Misaligned Operand References
Address10 Size Bus Additional Operations CR/W
14. Move Byte and Word Execution Times
Move Instruction Execution Times
15. Move Long Execution Times
Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wl
16. One Operand Instruction Execution Times
Standard One Operand Instruction Execution Times
Effective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx
17. Two Operand Instruction Execution Times
Standard Two Operand Instruction Execution Times
18. Miscellaneous Instruction Execution Times
Miscellaneous Instruction Execution Times
Opcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx
19. General Branch Instruction Execution Times
Branch Instruction Execution Times
20. Bcc Instruction Execution Times
Attribute
Chapter Interrupt Controller CF1INTC
HCS08
Interrupt Controller CF1INTC
V1 ColdFire Exception Vector Table
0x148 Next ACMPx 0x14C
0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x144
0x150 Next SCI2rx 0x154 SCI2tx 0x158
0x180 Next
To V1 ColdFire core
Interrupt Source Number
Freescale Semiconductor 177
Memory Map and Register Definition
External Signal Description
Modes of Operation
Intc Force Interrupt Register Intcfrc
Memory Map
CF1INTC Memory Map
Intcfrc Field Descriptions
INTCPL6P7,6 Field Descriptions
Intc Wake-up Control Register Intcwcr
Freescale Semiconductor 181
Intcwcr Field Descriptions
Intc Set Interrupt Force Register Intcsfrc
ENB
Intcsfrc Field Descriptions
Intc Clear Interrupt Force Register Intccfrc
Intccfrc Field Descriptions
Offset CF1INTCBASE + 0x1F Intccfrc
Vecn Swiack
Intc Software and Level-nIACK Registers n = 1,2,3,...,7
INTCSWIACK, INTCLVLnIACK Field Descriptions
Interrupt Request Level and Priority Assignments
10. Legend for Table
Priority within Level Midpoint
TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovfl
12. V1 ColdFire Interrupt Assignments
TPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl
Handling of Non-Maskable Level 7 Interrupt Requests
Application Information
Initialization Information
Emulation of the HCS08’s 1-Level IRQ Handling
More on Software IACKs
Using INTCPL6P7,6 Registers
Freescale Semiconductor 189
ISR Code Snippet with Swiack
Freescale Semiconductor 191
192 Freescale Semiconductor
Freescale Semiconductor 193
Chapter Rapid Gpio Rgpio
V1 ColdFire Core
Freescale Semiconductor 195
Core
IFP
OEP Dsoc
RAM Rgpio
Module
Rgpio
Pin Muxing + Pad Logic On-platform Bus
RGPIODATA150
Rgpio Module External I/O Signals
Detailed Signal Descriptions
Rgpio Detailed Signal Descriptions
Rgpio Write Memory Map
Memory Map/Register Definition
Rgpio Read Memory Map
Rgpio Data Rgpiodata
Rgpio Data Direction Rgpiodir
Rgpiodir Field Descriptions
DIR
Rgpio Clear Data Rgpioclr
Rgpio Pin Enable Rgpioenb
Rgpio Toggle Data Rgpiotog
Rgpio Set Data Rgpioset
Rgpioclr Field Descriptions
Rgpioset Field Descriptions
10. Rgpiotog Field Descriptions
Application 1 Simple Square-Wave Generation
TOG
Field Description 15-0 Rgpio Toggle Data
Peripheral Bus-mapped Gpio
11. Square-Wave Output Performance
Loop
Frequency @ Relative
SPI Speed @ Relative CPU f = 50 MHz
12. Emulated SPI Performance using Gpio Outputs
00x
29x
206 Freescale Semiconductor
ACMP/TPM Configuration Information
Acmp Configuration Information
Chapter Analog Comparator 3V ACMPVLPV1
Acmp Clock Gating
Interrupt Vectors
Freescale Semiconductor 209
210 Freescale Semiconductor
Wait Mode Operation
Block Diagram
Stop3 Mode Operation
Stop2 Mode Operation
Status and Control Register ACMPxSC
Register Definition
Acbgs Acpe
Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACF
ACMPxSC Field Descriptions
Interrupts
Acme
Acmod
214 Freescale Semiconductor
ADC Clock Gating
Chapter Analog-to-Digital Converter S08ADC12V1
Freescale Semiconductor 215
Analog-to-Digital Converter S08ADC12V1
Channel Assignments
Module Configurations
Alternate Clock
ADC Channel Assignment
Hardware Trigger
Temperature Sensor
Freescale Semiconductor 219
2provides a block diagram of the ADC module
Name Function
Signal Properties
AD27-AD0
Analog Ground Vssad
Analog Power Vddad
Voltage Reference High Vrefh
Voltage Reference Low Vrefl
Input Channel Select
Coco
Input Select
Data Result High Register Adcrh
Status and Control Register 2 ADCSC2
ADCSC2 Register Field Descriptions
Adact
Compare Value High Register Adccvh
Data Result Low Register Adcrl
ADR10 ADR9 ADR8
ADCV11 ADCV10 ADCV9 ADCV8
Compare Value Low Register Adccvl
Configuration Register Adccfg
Adccfg Register Field Descriptions
Adlpc
Clock Divide Select
Pin Control 1 Register APCTL1
Conversion Modes
Input Clock Select
10. APCTL1 Register Field Descriptions
Pin Control 2 Register APCTL2
ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
11. APCTL2 Register Field Descriptions
Pin Control 3 Register APCTL3
ADPC15
ADPC23
ADPC21
12. APCTL3 Register Field Descriptions
ADPC20
ADPC16
Input Select and Pin Control
Clock Select and Divide Control
Hardware Trigger
Conversion Control
Completing Conversions
Initiating Conversions
Aborting Conversions
Freescale Semiconductor 231
Sample Time and Total Conversion Time
Power Control
13. Total Conversion Time vs. Control Conditions
Adiclk Adlsmp
Automatic Compare Function
MCU Wait Mode Operation
MCU Stop2 Mode Operation
MCU Stop3 Mode Operation
Stop3 Mode With Adack Disabled
Stop3 Mode With Adack Enabled
Initialization Sequence
ADC Module Initialization Example
Pseudo-Code Example
Freescale Semiconductor 235
Reset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No
External Pins and Routing
COCO=1?
Yes Read Adcrh Then Adcrl To Clear Coco Bit Continue
Analog Reference Pins
Analog Supply Pins
Analog Input Pins
Freescale Semiconductor 237
Sampling Error
Sources of Error
Pin Leakage Error
Noise-Induced Errors
Linearity Errors
Code Width and Quantization Error
Lsb =
Freescale Semiconductor 239
Code Jitter, Non-Monotonicity, and Missing Codes
Freescale Semiconductor 241
242 Freescale Semiconductor
Chapter Internal Clock Source S08ICSV3
Stop2 Mode Considerations
External Oscillator
Freescale Semiconductor 243
Internal Clock Source S08ICSV3
Freescale Semiconductor 245
246 Freescale Semiconductor
Freescale Semiconductor 247
HGO, RANGE, EREFS, ERCLKEN, Erefsten
2is the ICS block diagram
FLL Bypassed External Low Power Fbelp
FLL Bypassed Internal Low Power Fbilp
ICS Register Summary
Rdiv Irefs
ICSC1 Field Descriptions
ICS Control Register 1 ICSC1
Clks Rdiv Irefs Irclken Irefsten
Reference Divide Factor
ICS Trim Register Icstrm
ICS Control Register 2 ICSC2
ICSC2 Field Descriptions
Bdiv Range HGO Erefs Erclken Erefsten
Icstrm Field Descriptions
ICS Status and Control Icssc
Icssc Field Descriptions
DMX32 Irefst Clkst Oscinit FTRIM1 DRS
512 16 20 MHz
Reference range FLL factor DCO range
608 19.92 MHz
1024 32 40 MHz
FLL Engaged Internal FEI
Operational Modes
IREFS=1 CLKS=00 IREFS=0
IREFS=0 CLKS=10
FLL Engaged External FEE
FLL Bypassed Internal Low Power Fbilp
FLL Bypassed Internal FBI
FLL Bypassed External FBE
FLL Bypassed External Low Power Fbelp
Mode Switching
Bus Frequency Divider
Stop
DCO Maximum Frequency with 32.768 kHz Oscillator
Low Power Bit Usage
Internal Reference Clock
External Reference Clock
Local Clock
Fixed Frequency Clock
Chapter Inter-Integrated Circuit S08IICV2
Module Configuration
IIC1 Position Options
SOPT2IIC1PS
MCF51QE128 Series Block Diagram Highlighting the IIC Modules
Freescale Semiconductor 261
262 Freescale Semiconductor
SDA Serial Data Line
SCL Serial Clock Line
Freescale Semiconductor 263
IIC Frequency Divider Register Iicf
IIC Address Register Iica
Iica Field Descriptions
= Unimplemented or Reserved
Hold Time Values for 8 MHz Bus Speed
Iicf Field Descriptions
Hold Times μs
Mult ICR SDA
ICR SCL
IIC Divider and Hold Values
IICC1 Field Descriptions
IIC Control Register IICC1
Iics Field Descriptions
IIC Status Register Iics
TCF
IIC Control Register 2 IICC2
IIC Data I/O Register Iicd
Iicd Field Descriptions
Freescale Semiconductor 269
IICC2 Field Descriptions
IIC Protocol
Gcaen
Slave Address Transmission
Start Signal
Freescale Semiconductor 271
Repeated Start Signal
Stop Signal
Arbitration Procedure
Data Transfer
Handshaking
Clock Synchronization
Clock Stretching
Freescale Semiconductor 273
Master-Transmitter Addresses a Slave-Receiver
13.4.2 10-bit Address
Master-Receiver Addresses a Slave-Transmitter
General Call Address
Resets
Byte Transfer Interrupt
Address Detect Interrupt
276 Freescale Semiconductor
Module Initialization Slave
Initialization/Application Information
Module Initialization Master
Module Use
12. Typical IIC Interrupt Routine
Freescale Semiconductor 279
280 Freescale Semiconductor
ADC Hardware Trigger
Chapter Real-Time Counter S08RTCV1
RTC Clock Sources
RTC Modes of Operation
Interrupt Vector
Freescale Semiconductor 283
MCF51QE128 Block Diagram Highlighting RTC Block and Pins
Active Background Mode
LPO
RTC Register Summary
Erclk
Irclk
Rtcsc Field Descriptions
RTC Status and Control Register Rtcsc
RTC Prescaler Divide-by values
Rtif
RTC Modulo Register Rtcmod
RTC Counter Register Rtccnt
Rtccnt Field Descriptions
Rtcmod Field Descriptions
Prescaler Period
RTC Operation Example
Rtcps
KHz Internal Clock MHz External Clock Rtclks =
Rtccnt Rtif
Internal 1-kHz Clock Source RTC Clock Rtcps =
0x52 0x53 0x54 0x55 0x00 0x01
Freescale Semiconductor 289
290 Freescale Semiconductor
SCI Clock Gating
Chapter Serial Communications Interface S08SCIV4
Freescale Semiconductor 291
Serial Communications Interface S08SCIV4
Module Initialization
294 Freescale Semiconductor
Freescale Semiconductor 295
× Baud Rate Clock
SCI Transmitter Block Diagram
Freescale Semiconductor 297
SCI Receiver Block Diagram
SCIxBDH Field Descriptions
SCI Baud Rate Registers SCIxBDH, SCIxBDL
Lbkdie
SCIxBDL Field Descriptions
SCI Control Register 1 SCIxC1
Loops Sciswai Rsrc Wake ILT
Loops
SCIxC2 Field Descriptions
SCI Control Register 2 SCIxC2
TIE
Tdre Rdrf Idle
SCI Status Register 1 SCIxS1
No parity error
Framing error
Parity error
SCIxD
SCIxS2 Field Descriptions
SCI Status Register 2 SCIxS2
Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF
RXINV1
SCIxC3 Field Descriptions
SCI Control Register 3 SCIxC3
Txdir
TXINV1
Baud Rate Generation
SCI Data Register SCIxD
Freescale Semiconductor 305
Send Break and Queued Idle
Transmitter Functional Description
Data Sampling Technique
Receiver Functional Description
Break Character Length
BRK13
Idle-Line Wakeup
Receiver Wakeup Operation
Freescale Semiconductor 309
Interrupts and Status Flags
Loop Mode
Stop Mode Operation
Additional SCI Functions
15.3.5.1 8- and 9-Bit Data Modes
Freescale Semiconductor 311
Single-Wire Operation
312 Freescale Semiconductor
SPI Clock Gating
Chapter Serial Peripheral Interface S08SPIV3
Freescale Semiconductor 313
MCF51QE128 Block Diagram Highlighting SPI Block and Pins
Freescale Semiconductor 315
316 Freescale Semiconductor
SPI System Block Diagram
Block Diagrams
Freescale Semiconductor 317
SPI Module Block Diagram
Freescale Semiconductor 319
SPI Baud Rate Generation
Mosi Master Data Out, Slave Data
Spsck SPI Serial Clock
Miso Master Data In, Slave Data Out
SS Slave Select
SPI in Stop Modes
Modes of Operation
SPI Control Register 1 SPIxC1
SPIxC1 Field Descriptions
SPI Control Register 2 SPIxC2
Master Mode Slave Mode
SS Pin Function
Modfen Ssoe
SPI Baud Rate Register SPIxBR
SPI Stop in Wait Mode
SPIxC2 Register Field Descriptions
Modfen Bidiroe Spiswai
SPIxBR Register Field Descriptions
SPI Status Register SPIxS
Sppr
SPR
SPI Data Register SPIxD
SPI Clock Formats
Freescale Semiconductor 327
10. SPI Clock Formats Cpha =
11. SPI Clock Formats Cpha =
SPI Interrupts
Freescale Semiconductor 329
Mode Fault Detection
330 Freescale Semiconductor
TPM Clock Gating
Chapter Timer/Pulse-Width Modulator S08TPMV3
Freescale Semiconductor 331
Timer/Pulse-Width Modulator S08TPMV3
Freescale Semiconductor 333
334 Freescale Semiconductor
Freescale Semiconductor 335
336 Freescale Semiconductor
Freescale Semiconductor 337
TPM Block Diagram
Extclk
Signal Description
Extclk External Clock Source
TPMxCHn TPM Channel n I/O Pins
Freescale Semiconductor 339
High-True Pulse of an Edge-Aligned PWM
TPMxSC Field Descriptions
TPM Status and Control Register TPMxSC
TOF Toie Cpwms Clksb Clksa PS2 PS1
TOF
TPM-Clock-Source Selection
TPM Counter Registers TPMxCNTHTPMxCNTL
Prescale Factor Selection
Clksbclksa
TPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter
TPM Counter Modulo Registers TPMxMODHTPMxMODL
TPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter
Freescale Semiconductor 343
TPMxMOD158
TPM Channel n Status and Control Register TPMxCnSC
TPMxMOD70
CHnF CHnIE MSnB MSnA ELSnB ELSnA
TPMxCnSC Field Descriptions
MSnBMSnA ELSnBELSnA Mode Configuration
Mode, Edge, and Level Selection
Cpwms
Mode, Edge, and Level Selection
TPM Channel Value Registers TPMxCnVHTPMxCnVL
TPMxCnV158
TPMxCnV70
Counter Clock Source
Counter
Freescale Semiconductor 347
TPM Clock Source Selection
Counter Overflow and Modulo Reset
Manual Counter Reset
Channel Mode Selection
Input Capture Mode
Output Compare Mode
15. PWM Period and Pulse Width ELSnA=0
Edge-Aligned PWM Mode
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Center-Aligned PWM Mode
Description of Reset Operation
Reset Overview
General
Interrupt Local Source Description Enable
Timer Overflow Interrupt TOF Description
Description of Interrupt Operation
Interrupt Summary
Center-Aligned PWM Case
Channel Event Interrupt Description
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Chapter Version 1 ColdFire Debug CF1DEBUG
OEP
Version 1 ColdFire Core CF1Core
PST
Bkgd BDC
Debug Revision Summary
Modes of Operations
Revision
Csrhrl CSR2D1HRL
Command Type Flash
BDM Command Types
Core Status Command Set
BDM?
Debug Module Signals Description
External Signal Descriptions
BDM GO
ENBDM=1
Debug Module Memory Map
DRc Register Name Width Access Reset Value Section Bits
CPU
Configuration/Status Register CSR
Bstat FOF TRG Halt Bkpt HRL BKD IPW
CSR Field Descriptions
TRC DDC UHE BTB NPL IPI SSM FID DDH
TRC
Xcsr Reference Summary
Extended Configuration/Status Register Xcsr
Method Reference Details
Apcsc Apce
CPU Cstat Halt Stop Eseqc Clksw SEC Erase Enbdm
Xcsr
CPU State
SEC R
Eseqc W
Erase W
CSR2 Reference Summary
Configuration/Status Register 2 CSR2
Xcsr CSR2
Syncpc Interval
CSR2 Field Descriptions
Pstb Valid Data Locations Oldest to Newest
PSTBWA7
10. CSR3 Reference Summary
Configuration/Status Register 3 CSR3
Pstbss
Start Condition Stop Condition
BFC Bfcdiv DIV8
BDM Address Attribute Register Baar
BFCDIV8
SZM TTM TMM
Address Attribute Trigger Register Aatr
BDM memory commands Normal processor access Else Reserved
Signal of the processor’s local bus
Trigger Definition Register TDR
SZM
L2EA
L2ED
L2T L1T
L1EA
L2T
Program Counter Breakpoint/Mask Registers PBR0-3, Pbmr
Three bits disables the address breakpoint
No inversion Invert data breakpoint comparators
15. PBR0 Field Descriptions
Mask Reset
DRc 0x08 PBR0
DRc 0x09 Pbmr
17. Pbmr Field Descriptions
Address Breakpoint Registers ABLR, Abhr
Abhr
Ablr
19. Abhr Field Description
Data Breakpoint and Mask Registers DBR, Dbmr
21. Dbmr Field Descriptions
22. Access Size and Operand Data Location
Background Debug Mode BDM
Address1 Access Size Operand Location
Resulting Set of Possible Trigger Combinations
23. CPU Halt Sources
CPU Halt
Halt Source Halt Timing Description
Cpucrard =
Cpucrird =
Background Debug Serial Interface Controller BDC
BDM Communication Details
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15. BDC Host-to-Target Serial Bit Timing
16. BDC Target-to-Host Serial Bit Timing Logic
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BDM Command Set Descriptions
Memory Commands
Miscellaneous Commands
Core Register Commands
PST Trace Buffer Read Commands
CRG
24. BDM Command Code Field Descriptions
CRG CRN
VBR
25. BDM Command Summary
BDM Command Set Summary
Ackdisable
Ackenable
Readdreg
Readcreg
Readpstb
Writecreg
Syncpc
Enable host/target handshake protocol Always Available
Disable host/target handshake protocol Always Available
0x03
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Enter active background mode if enabled Non-intrusive
Xcsrsb
Target 0x16 Memory Data15-8 Memory data7-0
0x12 Memory data7-0
Target
0x12 Memory
Read CPU control register Active Background
No operation Non-intrusive
0xA0+CRN Host → Target Dreg data
Read debug control register Non-intrusive
0x30 Address23-0
Target Memory data7-0 Target → Host
0x35
0x31
0x39
0x50+CRN Host → Target Pstb data
Read Xcsr Status Byte Always Available
Read general-purpose CPU register Active Background
Read CSR2 Status Byte Always Available
Read CSR3 Status Byte Always Available
Write CPU control register Active Background
Synchronize PC to PST/DDATA Signals Non-intrusive
0xC0+CRN Creg data
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0x80+CRN Dreg data
Write debug control register Non-intrusive
0x10 Address23-0 Memory Data7-0
Host → target
Write general-purpose CPU register Active Background
Write Xcsr Status Byte Always Available
Serial Interface Hardware Handshake Protocol
Write CSR2 Status Byte Always Available
Write CSR3 Status Byte Always Available
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19. Target Acknowledge Pulse ACK
20. Handshake Protocol at Command Level
Hardware Handshake Abort Procedure
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21signal timing is not drawn to scale
21. ACK Abort Procedure at the Command Level
Real-Time Trace Support
Real-Time Debug Support
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26. Processor Status Encodings
Enter user mode
PST40 Definition
Instructions, generate different encodings
0x08-0x0B
Begin Execution of Taken Branch PST =
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PST Values Description
23. Example JMP Instruction Output in Pstb
18.4.3.3 PST/DDATA Example
PST Trace Buffer Pstb
Pstbpst
Pstbddata
Processor Status, Debug Data Definition
Instruction Operand Syntax
27. PST/DDATA Specification for User-Mode Instructions
PST/DDATA
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416 Freescale Semiconductor
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Supervisor Instruction Set
Freescale-Recommended BDM Pinout
GND Reset
No Connect
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420 Freescale Semiconductor
Changes between Rev and Rev
Appendix a Revision History
MCF51QE128RM Rev to Rev Changes
Chapter Description
Revision History
Page
How to Reach Us
PORT D
PORT E
