Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
MCF51QE128 MCU Series Reference Manual, Rev. 3
410 Freescale Semiconductor
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For the V1 ColdFire core and its single debug signal, support for trace functionality is completely
redefined. The V1 solution provides an on-chip PST/DDATA trace buffer (known as the PSTB) to record
the stream of PST and DDATA values.
Even with the application of a PST trace buffer, problems associated with the PST bandwidth and
associated fill rate of the buffer remain. Given that there is one (or more) PST entry per instruction, the
PSTB would fill rapidly without some type of data compression. Luckily, the PST compression technology
was previously developed and included as part of the Version 5 ColdFire core (although very different than
the resulting V1 implementation).
Consider the following example to illustrate the PST compression algorithm. Most sequential instructions
generate a single PST = 1 value. Without compression, the execution of ten sequential instructions
generates a stream of ten PST = 1 values. With PST compression, the reporting of any PST = 1 value is
delayed so that consecutive PST = 1 values can be accumulated. When a PST ≠1 value is reported, the
maximum accumulation count reached, or a debug data value captured, a single accumulated PST value is
generated. Returning to the example with compression enabled, the execution of ten sequential
instructions generates a single PST value indicating ten sequential instructions have been executed.
This technique has proven to be effective at significantly reducing the average PST entries per instruction
and PST entries per machine cycle. The application of this compression technique makes the application
of a useful PST trace buffer for the V1 ColdFire core realizable. The resulting 5-bit PST definitions are
shown in Table 18-26.
Table 18-26. Processor Status Encodings
PST[4:0] Definition
0x00 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
processor clock cycles, subsequent clock cycles are indicated by driving PST with this encoding.
0x01 Begin execution of one instruction. For most instructions, this encoding signals the first processor clock
cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
0x02 Reserved
0x03 Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
0x04 Begin execution of PULSE and WDDATA instructions. PULSE defines triggers or markers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the DDATA port, independent of debug module configuration. When WDDATA is executed, a
value of 0x04 is signaled on the PST port, followed by the appropriate marker, and then the data transfer
on the DDATA port. The number of captured data bytes depends on the WDDATA operand size.
0x05 Begin execution of taken branch or SYNC_PC BDM command. For some opcodes, a branch target
address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins
the data output. This encoding also indicates that the SYNC_PC command has been processed.
0x06 Reserved
0x07 Begin execution of return from exception (RTE) instruction.