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Freescale Semiconductor MCF51QE128RM Chapter 13 Inter-Integrated Circuit (S08IICV2)

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MCF51QE128 MCU Series Reference Manual, Rev. 3

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Chapter 13 Inter-Integrated Circuit (S08IICV2)

13.1 Introduction

The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The

interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is

capable of operating at higher baud rates, up to a maximum of bus clock/20, with reduced bus loading. The

maximum communication length and the number of devices that can be connected are limited by a

maximum bus capacitance of 400 pF.

All MCF51QE128 Series MCUs feature the one or two IICs, as shown in Figure 13-1.

NOTE

The SDA and SCL should not be driven above VDD. These pins are psuedo

open-drain containing a protection diode to VDD.

13.1.1 Module Configuration

The IIC1 module pins, SDA and SCL, can be repositioned under software control using SOPT2[IIC1PS]

as shown in Table 13-1. This bit selects which general-purpose I/O ports are associated with IIC1

operation.

13.1.2 Interrupt Vectors

For MCF51QE128 Series MCUs with two IICs, both IICs share a single interrupt vector. When interrupts

are enabled for both IICs, the IICF bit must be polled in the IIC1S and IIC2S registers to determine which

IIC caused the interrupt. See Chapter 8, “Interrupt Controller (CF1_INTC),” for the IIC interrupt vector

assignment.

Table 13-1. IIC1 Position Options

SOPT2[IIC1PS] Port Pin for SDA Port Pin for SCL

0 (default) PTA2 PTA3

1 PTB6 PTB7

Contents

Main Page MCF51QE128 Series Features Page Page Contents Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation Chapter 4 Memory Chapter 5 Resets, Interrupts, and General System Control Chapter 6 Parallel Input/Output Control Page Chapter 7 ColdFire Core Chapter 8 Interrupt Controller (CF1_INTC) Chapter 9 Rapid GPIO (RGPIO) Chapter 10 Analog Comparator 3V (ACMPVLPV1) Chapter 11 Analog-to-Digital Converter (S08ADC12V1) Page Chapter 12 Internal Clock Source (S08ICSV3) Chapter 13 Inter-Integrated Circuit (S08IICV2) Chapter 14 Real-Time Counter (S08RTCV1) Chapter 15 Serial Communications Interface (S08SCIV4) Chapter 16 Serial Peripheral Interface (S08SPIV3) Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) Appendix A Revision History Chapter 1 Device Overview 1.1 Devices in the MCF51QE128/64/32 Series Table 1-1 summarizes the feature set available in the MCF51QE128/64/32 series of MCUs. 1.2 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MCF51QE128/64/32 MCU. Table 1-1. MCF51QE128 Series Features by MCU and Package (continued) Chapter 1 Device Overview PORT A Figure 1-1. MCF51QE128/64/32 Block Diagram 1.3 V1 ColdFire Core 1.4 System Clocks 1.4.1 Internal Clock Source (ICS) Module 1.4.2 System Clock Distribution Page 1.4.3 ICS Modes of Operation 1.4.3.1 FLL Engaged Internal (FEI) 1.4.3.2 FLL Engaged External (FEE) 1.4.3.3 FLL Bypassed Internal (FBI) 1.4.3.4 FLL Bypassed Internal Low-Power (FBILP) 1.4.3.6 FLL Bypassed External Low-Power (FBELP) 1.4.3.7 Stop (STOP) Page Page Page 34 Freescale Semiconductor Chapter 2 Pins and Connections Figure 2-1. 80-Pin LQFP Pins in bold are added from the next smaller package. Chapter 2 Pins and Connections Figure 2-2. 64-Pin LQFP 2.2 Recommended System Connections Figure 2-3 shows pin connections common to MCF51QE128/64/32 application systems. Figure 2-3. Basic System Connections 2.2.1 Power 2.2.2 Oscillator 2.2.3 RESET and RSTO 2.2.4 Background / Mode Select (BKGD/MS) 2.2.5 ADC Reference Pins (VREFH, VREFL) 2.2.6 General-Purpose I/O and Peripheral Ports 40 Freescale Semiconductor Table 2-1. Pin Assignment by Package and Pin Sharing Priority Pin Number Lowest Priority Highest 80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4 Freescale Semiconductor 41 Get the latest version from freescale.com SOPT2[SPI1PS]. Default locations are PTB5, PTB4, PTB3, and PTB2, respectively. Table 2-1. Pin Assignment by Package and Pin Sharing Priority (continued) Pin Number Lowest Priority Highest 80 64 Port Pin Alt 1 Alt 2 Alt 3 Alt 4 Page Chapter 3 Modes of Operation 3.1 Introduction 3.2 Features 3.3 Overview Freescale Semiconductor 45 Chapter 3 Modes of Operation 2250 kHz maximum CPU frequency in LPrun; 125 kHz maximum peripheral clock frequency. Section 18.3.2, Extended Configuration/Status Register (XCSR). Table 3-1. CPU / Power Mode Selections Page Figure 3-3. All Allowable Power Mode Transitions for MCF51QE128/64/32 Tabl e 3-2 defines triggers for the various state transitions shown in Figure 3-2. Tabl e 3-2 . Tri gger s for Trans iti ons S hown in Figure 3-2 3.4 Debug Mode 3.5 Secure Mode 3.6 Run Modes 3.6.1 Run Mode 3.6.2 Low -Power Run Mode (LPrun) 3.6.2.1 BDM in Low-Power Run Mode 3.7 Wait Modes 3.7.1 Wait Mode 3.7.2 Low-Power Wait Mode (LPwait) 3.7.2.1 BDM in Low-Power Wait Mode 3.8 Stop Modes 3.8.1 Stop2 Mode 3.8.1.1 Low-Range Oscillator Considerations for Stop2 3.8.2 Stop3 Mode 3.8.3 Stop4: Low Voltage Detect or BDM Enabled in Stop Mode 3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes Table 3-4. Low-Power Mode Behavior (continued) Page Page Chapter 4 Memory 4.1 MCF51QE128/64/32 Memory Map Figure 4-1. MCF51QE128/64/32 Memory Maps MCF51QE128 MCF51QE64 4.2 Register Addresses and Bit Assignments Page Table4-2. Direct-Page Register Summary (Sheet 1 of 4) Table4-2. Direct-Page Register Summary (Sheet 2 of 4) Table4-2. Direct-Page Register Summary (Sheet 3 of 4) Table 4-3. High-Page Register Summary (Sheet 1 of 5) Table4-2. Direct-Page Register Summary (Sheet 4 of 4) Table 4-3. High-Page Register Summary (Sheet 2 of 5) Table 4-3. High-Page Register Summary (Sheet 3 of 5) Table 4-3. High-Page Register Summary (Sheet 4 of 5) 4.2.1 Flash Module Reserved Memory Locations Page 4.2.2 ColdFire Rapid GPIO Memory Map 4.2.3 ColdFire Interrupt Controller Memory Map Table 4-6. V1 ColdFire Rapid GPIO Memory Map Table 4-7. V1 ColdFire Interrupt Controller Memory Map 4.3 RAM 4.4 Flash 4.4.1 Features 4.4.2 Register Descriptions 4.4.2.1 Flash Clock Divider Register (FCDIV) 4.4.2.2 Flash Options Register (FOPT and NVOPT) 4.4.2.3 Flash Configuration Register (FCNFG) 4.4.2.4 Flash Protection Register (FPROT and NVPROT) Table 4-13. Flash Protection Address Range (continued) 4.4.2.5 Flash Status Register (FSTAT) Figure 4-7. Flash Status Register (FSTAT) Table 4-14. FSTAT Field Descriptions 4.4.2.6 Flash Command Register (FCMD) 4.5 Function Description 4.5.1 Flash Command Operations 4.5.1.1 Writing the FCDIV Register 4.5.1.2 Command Write Sequence 4.5.2 Flash Commands 4.5.2.1 Erase Verify Command Figure 4-10. Example Erase Verify Command Flow 4.5.2.2 Program Command Figure 4-11. Example Program Command Flow 4.5.2.3 Burst Program Command Figure 4-12. Example Burst Program Command Flow 4.5.2.4 Sector Erase Command Figure 4-13. Example Sector Erase Command Flow 4.5.2.5 Mass Erase Command Figure 4-14. Example Mass Erase Command Flow NOTE 4.5.3 Illegal Flash Operations 4.5.3.1 Flash Access Violations 4.5.3.2 Flash Protection Violations 4.5.4 Operating Modes 4.5.4.1 Wait Mode 4.5.4.2 Stop Modes 4.5.4.3 Background Debug Mode 4.5.5 Security 4.5.5.1 Unsecuring the MCU using Backdoor Key Access 4.5.6 Resets 4.5.6.1 Flash Reset Sequence 4.5.6.2 Reset While Flash Command Active 4.5.6.3 Program and Erase Times 4.6 Security Figure 4-15. Procedure for Clearing Security on MCF51QE128/64/32 via the BDM Port Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction 5.2 Features 5.3 Microcontroller Reset 5.3.1 Computer Operating Properly (COP) Watchdog 5.3.2 Illegal Operation Reset 5.3.3 Illegal Address Reset 5.4 Interrupts and Exceptions 5.4.1 External Interrupt Request (IRQ) Pin 5.4.1.1 Pin Configuration Options 5.4.1.2 Edge and Level Sensitivity 5.4.1.3 External Interrupt Initialization 5.5 Low-Voltage Detect (LVD) System 5.5.1 Power-On Reset Operation 5.5.2 LVD Reset Operation 5.5.3 LVD Interrupt Operation 5.5.4 Low-Voltage Warning (LVW) Interrupt Operation 5.6 Peripheral Clock Gating 5.7 Reset, Interrupt, and System Control Registers and Control Bits 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) 5.7.2 System Reset Status Register (SRS) Figure 5-2. System Reset Status (SRS) Table 5-3. SRS Register Field Descriptions Table 5-2. IRQSC Register Field Descriptions (continued) 5.7.3 System Options Register 1 (SOPT1) Figure 5-3. System Options Register 1 (SOPT1) Table 5-3. SRS Register Field Descriptions (continued) 5.7.4 System Options Register 2 (SOPT2) Figure 5-4. System Options Register 2 (SOPT2) Table 5-4. SOPT1 Register Field Descriptions 5.7.5 System Device Identification Register (SDIDH, SDIDL) Table 5-5. SOPT2 Register Field Descriptions 5.7.6 System Power Management Status and Control 1 Register (SPMSC1) Figure 5-7. System Power Management Status and Control 1 Register (SPMSC1) 5.7.7 System Power Management Status and Control 2 Register (SPMSC2) Figure 5-8. System Power Management Status and Control 2 Register (SPMSC2) SPMSC2 is not reset when exiting from stop2. Table 5-8. SPMSC1 Register Field Descriptions 5.7.8 System Power Management Status and Control 3 Register (SPMSC3) Table 5-9. SPMSC2 Register Field Descriptions Table 5-11. L VD and LVW Trip Point T ypical Values 5.7.9 System Clock Gating Control 1 Register (SCGC1) 5.7.10 System Clock Gating Control 2 Register (SCGC2) Page Page Page Page Page Chapter 6 Parallel Input/Output Control 6.1 Port Data and Data Direction 6.2 Pull-up, Slew Rate, and Drive Strength 6.2.1 Port Internal Pull-up Enable 6.2.2 Port Slew Rate Enable 6.2.3 Port Drive Strength Select 6.3 Port Data Set, Clear and Toggle Data Registers 6.3.1 Port Data Set Registers 6.3.2 Port Data Clear Registers 6.3.3 Port Data Toggle Register 6.4 V1 ColdFire Rapid GPIO Functionality 6.5 Keyboard Interrupts 6.5.1 Edge Only Sensitivity 6.5.2 Edge and Level Sensitivity 6.5.3 Pull-up/Pull-down Resistors 6.5.4 Keyboard Interrupt Initialization 6.6 Pin Behavior in Stop Modes 6.7 Parallel I/O, Keyboard Interrupt, and Pin Control Registers 6.7.1 Port A Registers 6.7.1.1 Port A Data Register (PTAD) 6.7.1.2 Port A Data Direction Register (PTADD) 6.7.1.3 Port A Pull Enable Register (PTAPE) Figure 6-4. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Figure 6-5. Port A Data Direction Register (PTADD) Table 6-2. PTADD Register Field Descriptions 6.7.1.4 Port A Slew Rate Enable Register (PTASE) 6.7.1.5 Port A Drive Strength Selection Register (PTADS) Figure 6-8. Drive Strength Selection for Port A Register (PTADS) 6.7.2 Port B Registers Port B is controlled by the registers listed below. Figure 6-10. Port B Data Direction Register (PTBDD) 6.7.2.2 Port B Data Direction Register (PTBDD) 6.7.2.1 Port B Data Register (PTBD) 6.7.2.3 Port B Pull Enable Register (PTBPE) 6.7.2.4 Port B Slew Rate Enable Register (PTBSE) Table 6-7. PTBDD Register Field Descriptions 6.7.2.5 Port B Drive Strength Selection Register (PTBDS) 6.7.3 Port C Registers 6.7.3.1 Port C Data Register (PTCD) Port C is controlled by the registers listed below. Figure 6-14. Port C Data Register (PTCD) Table 6-11. PTCD Register Field Descriptions 6.7.3.2 Port C Data Direction Register (PTCDD) 6.7.3.3 Port C Data Set Register (PTCSET) Figure 6-17. Port C Data Clear Register (PTCCLR) 6.7.3.4 Port C Data Clear Register (PTCCLR) Figure 6-15. Port C Data Direction Register (PTCDD) Table 6-12. PTCDD Register Field Descriptions 6.7.3.5 Port C Toggle Register (PTCTOG) 6.7.3.6 Port C Pull Enable Register (PTCPE) Table 6-14. PTCCLR Register Field Descriptions Figure 6-18. Port C Toggle Enable Register (PTCTOG) Table 6-15. PTCTOG Register Field Descriptions 6.7.3.7 Port C Slew Rate Enable Register (PTCSE) 6.7.4 Port D Registers Port D is controlled by the registers listed below. 6.7.4.2 Port D Data Direction Register (PTDDD) 6.7.4.3 Port D Pull Enable Register (PTDPE) Table 6-19. PTDD Register Field Descriptions Figure 6-23. Port D Data Direction Register (PTDDD) Table 6-20. PTDDD Register Field Descriptions 6.7.4.4 Port D Slew Rate Enable Register (PTDSE) 6.7.5 Port E Registers Port E is controlled by the registers listed below. 6.7.5.2 Port E Data Direction Register (PTEDD) 6.7.5.3 Port E Data Set Register (PTESET) Table 6-24. PTED Register Field Descriptions Figure 6-28. Port E Data Direction Register (PTEDD) Table 6-25. PTEDD Register Field Descriptions Figure 6-29. Port E Data Set Register (PTESET) Table 6-26. PTESET Register Field Descriptions 6.7.5.4 Port E Data Clear Register (PTECLR) 6.7.5.5 Port E Toggle Register (PTETOG) Figure 6-32. Internal Pull Enable for Port E Register (PTEPE) 6.7.5.6 Port E Pull Enable Register (PTEPE) Figure 6-30. Port E Data Clear Register (PTECLR) Table 6-27. PTECLR Register Field Descriptions 6.7.5.7 Port E Slew Rate Enable Register (PTESE) 6.7.5.8 Port E Drive Strength Selection Register (PTEDS) Table 6-29. PTEPE Register Field Descriptions 6.7.6 Port F Registers Port F is controlled by the registers listed below. 6.7.6.1 Port F Data Register (PTFD) 6.7.6.2 Port F Data Direction Register (PTFDD) 6.7.6.3 Port F Pull Enable Register (PTFPE) 6.7.6.4 Port F Slew Rate Enable Register (PTFSE) 6.7.6.5 Port F Drive Strength Selection Register (PTFDS) Figure 6-39. Drive Strength Selection for Port F Register (PTFDS) 6.7.7 Port G Registers Port G is controlled by the registers listed below. 6.7.7.2 Port G Data Direction Register (PTGDD) 6.7.7.1 Port G Data Register (PTGD) Table 6-36. PTFDS Register Field Descriptions 6.7.7.3 Port G Pull Enable Register (PTGPE) Figure 6-44. Drive Strength Selection for Port G Register (PTGDS) 6.7.7.5 Port G Drive Strength Selection Register (PTGDS) 6.7.7.4 Port G Slew Rate Enable Register (PTGSE) 6.7.8 Port H Registers Port H is controlled by the registers listed below. 6.7.8.2 Port H Data Direction Register (PTHDD) 6.7.8.1 Port H Data Register (PTHD) Table 6-41. PTGDS Register Field Descriptions 6.7.8.3 Port H Pull Enable Register (PTHPE) Figure 6-49. Drive Strength Selection for Port H Register (PTHDS) 6.7.8.5 Port H Drive Strength Selection Register (PTHDS) 6.7.8.4 Port H Slew Rate Enable Register (PTHSE) 6.7.9 Port J Registers Port J is controlled by the registers listed below. 6.7.9.2 Port J Data Direction Register (PTJDD) 6.7.9.1 Port J Data Register (PTJD) Table 6-46. PTHDS Register Field Descriptions 6.7.9.3 Port J Pull Enable Register (PTJPE) Figure 6-54. Drive Strength Selection for Port J Register (PTJDS) 6.7.9.5 Port J Drive Strength Selection Register (PTJDS) 6.7.9.4 Port J Slew Rate Enable Register (PTJSE) 6.7.10 Keyboard Interrupt 1 (KBI1) Registers 6.7.10.1 KBI1 Interrupt Status and Control Register (KBI1SC) Table 6-51. PTJDS Register Field Descriptions Table 6-52. KBI1 Pin Mapping 6.7.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) 6.7.11 Keyboard Interrupt 1 (KBI2) Registers Figure 6-57. KBI1 Edge Select Register (KBI1ES) Table 6-55. KBI1ES Register Field Descriptions Table 6-56. KBI2 Pin Mapping 6.7.11.1 KBI2 Interrupt Status and Control Register (KBI2SC) 6.7.11.2 KBI2 Interrupt Pin Select Register (KBI2PE) 6.7.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) Figure 6-60. KBI2 Edge Select Register (KBI2ES) Table 6-59. KBI2ES Register Field Descriptions Page Chapter 7 ColdFire Core 7.1 Introduction 7.1.1 Overview Figure 7-1. V1 ColdFire Core Pipelines 7.2 Memory Map/Register Description 7.2.1 Data Registers (D0D7) Table 7-1. ColdFire Core Programming Model 7.2.2 Address Registers (A0A6) 7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) 7.2.4 Condition Code Register (CCR) 7.2.5 Program Counter (PC) 7.2.6 Vector Base Register (VBR) Figure 7-7. Vector Base Register (VBR) 7.2.7 CPU Configuration Register (CPUCR) Figure 8. CPU Configuration Register (CPUCR) Table 3. CPUCR Field Descriptions 7.2.8 Status Register (SR) Figure 7-9. Status Register (SR) Table 7-4. SR Field Descriptions Table 3. CPUCR Field Descriptions (continued) 7.3 Functional Description 7.3.1 Instruction Set Architecture (ISA_C) 7.3.2 Exception Processing Overview Page 7.3.2.1 Exception Stack Frame Definition 7.3.2.2 S08 and ColdFire Exception Processing Comparison Page 7.3.3 Processor Exceptions 7.3.3.1 Access Error Exception 7.3.3.2 Address Error Exception 7.3.3.3 Illegal Instruction Exception 7.3.3.4 Privilege Violation 7.3.3.5 Trace Exception 7.3.3.6 Unimplemented Line-A Opcode 7.3.3.7 Unimplemented Line-F Opcode 7.3.3.8 Debug Interrupt 7.3.3.9 RTE and Format Error Exception 7.3.3.10 TRAP Instruction Exception 7.3.3.11 Unsupported Instruction Exception 7.3.3.12 Interrupt Exception 7.3.3.13 Fault-on-Fault Halt 7.3.3.14 Reset Exception Table 7-11. D0 Hardware Configuration Info Field Description Page 7.3.4 Instruction Execution Timing 7.3.4.1 Timing Assumptions 7.3.4.2 MOVE Instruction Execution Times Table 7-14 lists execution times for MOVE.{B,W} instructions; Table7-15 lists timings for MOVE.L. Table 7-14. MOVE Byte and Word Execution Times Table 7-15. MOVE Long Execution Times 7.3.4.3 Standard One Operand Instruction Execution Times Table 7-16. One Operand Instruction Execution Times Table 7-15. MOVE Long Execution Times (continued) 7.3.4.4 Standard Two Operand Instruction Execution Times Table 7-17. Two Operand Instruction Execution Times 7.3.4.5 Miscellaneous Instruction Execution Times Table 7-18. Miscellaneous Instruction Execution Times Table 7-17. Two Operand Instruction Execution Times (continued) 7.3.4.6 Branch Instruction Execution Times Table 7-19. General Branch Instruction Execution Times Table 7-20. Bcc Instruction Execution Times Table7 -18. Miscellaneous Instruction Execution Times (continued) Chapter 8 Interrupt Controller (CF1_INTC) 8.1 Introduction 8.1.1 Overview Page Table 8-2. V1 ColdFire Exception Vector Table (continued) 8.1.2 Features 8.1.3 Modes of Operation 8.2 External Signal Description 8.3 Memory Map and Register Definition 8.3.1 Memory Map 8.3.2 Register Descriptions 8.3.2.1 INTC Force Interrupt Register (INTC_FRC) Figure 8-2. INTC_FRC Register 8.3.2.2 INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}) Table 8-4. INTC_FRC Field Descriptions 8.3.2.3 INTC Wake-up Control Register (INTC_WCR) 8.3.2.4 INTC Set Interrupt Force Register (INTC_SFRC) 8.3.2.5 INTC Clear Interrupt Force Register (INTC_CFRC) Figure 8-6. INTC_CFRC Register Table 8-7. INTC_SFRC Field Descriptions Table 8-8. INTC_CFRC Field Descriptions 8.3.2.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) 8.3.3 Interrupt Request Level and Priority Assignments Table 8-9. INTC_SWIACK, INTC_LVLnIACK Field Descriptions Table 8-10. Legend for Table 8 -11 Table 8-11. V1 ColdFire [Level][Priority within Level] Matrix Interrupt Assignments Table 8-12. V1 ColdFire Interrupt Assignments Table 8-11. V1 ColdFire [Level][Priority within Level] Matrix Interrupt Assignments (continued) 8.4 Functional Description 8.4.1 Handling of Non-Maskable Level 7 Interrupt Requests Table 8-12. V1 ColdFire Interrupt Assignments (continued) 8.5 Initialization Information 8.6 Application Information 8.6.1 Emulation of the HCS08s 1-Level IRQ Handling 8.6.2 Using INTC_PL6P{7,6} Registers 8.6.3 More on Software IACKs Page Page Page Chapter 9 Rapid GPIO (RGPIO) 9.1 Introduction Chapter 9 Rapid GPIO (RGPIO) PORT A PORT G Figure 9-1. MCF51QE128 Series Block Diagram Highlighting RGPIO Block and Pins 9.1.1 Overview Figure 9-2. V1 ColdFire Block Diagram 9.1.2 Features 9.1.3 Modes of Operation 9.2 External Signal Description 9.2.1 Overview 9.2.2 Detailed Signal Descriptions 9.3 Memory Map/Register Definition 9.3.1 Memory Map 9.3.2 Register Descriptions 9.3.2.1 RGPIO Data Direction (RGPIO_DIR) 9.3.2.2 RGPIO Data (RGPIO_DATA) Figure 9-5. RGPIO Data Register (RGPIO_DATA) 9.3.2.3 RGPIO Pin Enable (RGPIO_ENB) Figure 9-6. RGPIO Enable Register (RGPIO_ENB) 9.3.2.4 RGPIO Clear Data (RGPIO_CLR) Table 9-6. RGPIO_DATA Field Descriptions Table 9-7. RGPIO_ENB Field Descriptions 9.3.2.5 RGPIO Set Data (RGPIO_SET) 9.3.2.6 RGPIO Toggle Data (RGPIO_TOG) 9.4 Functional Description 9.5 Initialization Information 9.6 Application Information 9.6.1 Application 1: Simple Square-Wave Generation 9.6.2 Application 2: 16-bit Message Transmission using SPI Protocol Figure 9-11. GPIO SPI Code Example Table 9-12. Emulated SPI Performance using GPIO Outputs Page Chapter 10 Analog Comparator 3V (ACMPVLPV1) 10.1 Introduction 10.1.1 ACMP Configuration Information 10.1.2 ACMP/TPM Configuration Information 10.1.3 ACMP Clock Gating Page Chapter 10 Analog Comparator 3V (ACMPVLPV1) PORT A PORT G PORT F Figure 10-1. MCF51QE128 Series Block Diagram Highlighting ACMP Block and Pins Page 10.1.5 Features 10.1.6 Modes of Operation 10.1.6.1 Wait Mode Operation 10.1.6.2 Stop3 Mode Operation 10.1.6.3 Stop2 Mode Operation 10.2 External Signal Description 10.3 Register Definition 10.3.1 Status and Control Register (ACMPxSC) Figure 10-3. ACMP Status and Control Register (ACMPxSC) + 10.4 Functional Description 10.5 Interrupts Table 10-1. ACMPxSC Field Descriptions Page Chapter 11 Analog-to-Digital Converter (S08ADC12V1) 11.1 Introduction 11.1.1 ADC Clock Gating Chapter 11 Analog-to-Digital Converter (S08ADC12V1) PORT A Figure 11-1. MCF51QE128 Series Block Diagram Highlighting ADC Block and Pins 11.1.2 Module Configurations 11.1.2.1 Channel Assignments 11.1.2.2 Alternate Clock 11.1.2.3 Hardware Trigger 11.1.2.4 Temperature Sensor 11.1.3 Interrupt Vectors 11.1.4 Features 11.1.5 Block Diagram Analog-to-Digital Converter (S08ADC12V1) 220 Freescale Semiconductor Get the latest version from freescale.com ADCSC2 11.2 External Signal Description Table 11-2. Signal Properties AD0 AD27 V V 11.3 Register Definition 11.3.1 Status and Control Register 1 (ADCSC1) Figure 11-3. Status and Control Register (ADCSC1) Table 11-3. ADCSC1 Field Descriptions Table11-4. Input Channel Select 11.3.2 Status and Control Register 2 (ADCSC2) 11.3.3 Data Result High Register (ADCRH) Figure 11-4. Status and Control Register 2 (ADCSC2) Table 11-5. ADCSC2 Register Field Descriptions 11.3.4 Data Result Low Register (ADCRL) 11.3.5 Compare Value High Register (ADCCVH) 11.3.6 Compare Value Low Register (ADCCVL) 11.3.7 Configuration Register (ADCCFG) 11.3.8 Pin Control 1 Register (APCTL1) The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is Table11-7. Clock Divide Select Table 11-8. Conversion Modes Table 11-9. Input Clock Select 11.3.9 Pin Control 2 Register (APCTL2) Figure 11-11. Pin Control 2 Register (APCTL2) APCTL2 controls channels 815 of the ADC module. Figure 11-10. Pin Control 1 Register (APCTL1) Table 11-10. APCTL1 Register Field Descriptions 11.3.10 Pin Control 3 Register (APCTL3) APCTL3 controls channels 1623 of the ADC module. Figure 11-12. Pin Control 3 Register (APCTL3) Table 11-11. APCTL2 Register Field Descriptions 11.4 Functional Description 11.4.1 Clock Select and Divide Control 11.4.2 Input Select and Pin Control 11.4.3 Hardware Trigger 11.4.4 Conversion Control 11.4.4.1 Initiating Conversions 11.4.4.2 Completing Conversions 11.4.4.3 Aborting Conversions 11.4.4.4 Power Control 11.4.4.5 Sample Time and Total Conversion Time 11.4.5 Automatic Compare Function 11.4.6 MCU Wait Mode Operation 11.4.7 MCU Stop3 Mode Operation 11.4.7.1 Stop3 Mode With ADACK Disabled 11.4.7.2 Stop3 Mode With ADACK Enabled 11.5 Initialization Information 11.5.1 ADC Module Initialization Example 11.5.1.1 Initialization Sequence 11.5.1.2 Pseudo-Code Example 11.6 Application Information 11.6.1 External Pins and Routing 11.6.1.1 Analog Supply Pins 11.6.1.2 Analog Reference Pins 11.6.1.3 Analog Input Pins 11.6.2 Sources of Error 11.6.2.1 Sampling Error 11.6.2.2 Pin Leakage Error 11.6.2.3 Noise-Induced Errors 11.6.2.4 Code Width and Quantization Error 11.6.2.5 Linearity Errors 11.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes Page Page Chapter 12 Internal Clock Source (S08ICSV3) 12.1 Introduction 12.1.1 External Oscillator 12.1.2 Stop2 Mode Considerations Chapter 12 Internal Clock Source (S08ICSV3) Figure 12-1. MCF51QE128 Series Block Diagram Highlighting ICS Block and Pins Page Page 12.1.3 Features 12.1.4 Block Diagram Figure 12-2 is the ICS block diagram. Figure 12-2. Internal Clock Source (ICS) Block Diagram 12.1.5 Modes of Operation There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop. 12.2 External Signal Description 12.3 Register Definition 12.3.1 ICS Control Register 1 (ICSC1) 12.3.2 ICS Control Register 2 (ICSC2) 12.3.3 ICS Trim Register (ICSTRM) Figure 12-5. ICS Trim Register (ICSTRM) Figure 12-4. ICS Control Register 2 (ICSC2) Table 12-4. ICSC2 Field Descriptions 12.3.4 ICS Status and Control (ICSSC) Table 12-5. ICSTRM Field Descriptions Figure 12-6. ICS Status and Control Register (ICSSC) Table 12-6. ICSSC Field Descriptions Page 12.4 Functional Description 12.4.1 Operational Modes Figure 12-7. Clock Switching Modes 12.4.1.1 FLL Engaged Internal (FEI) 12.4.1.2 FLL Engaged External (FEE) 12.4.1.3 FLL Bypassed Internal (FBI) 12.4.1.4 FLL Bypassed Internal Low Power (FBILP) 12.4.1.5 FLL Bypassed External (FBE) 12.4.1.6 FLL Bypassed External Low Power (FBELP) 12.4.2 Mode Switching 12.4.3 Bus Frequency Divider 12.4.4 Low Power Bit Usage 12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator 12.4.6 Internal Reference Clock 12.4.7 External Reference Clock Page Chapter 13 Inter-Integrated Circuit (S08IICV2) 13.1 Introduction 13.1.1 Module Configuration 13.1.2 Interrupt Vectors Chapter 13 Inter-Integrated Circuit (S08IICV2) Figure 13-1. MCF51QE128 Series Block Diagram Highlighting the IIC Modules Page 13.1.3 Features 13.1.4 Modes of Operation Freescale Semiconductor 2-263 13.1.5 Block Diagram Figure 13-2 is a block diagram of the IIC. 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.1 SCL Serial Clock Line The bidirectional SCL is the serial clock line of the IIC system. 13.2.2 SDA Serial Data Line 13.3.1 IIC Address Register (IICA) Figure 13-4. IIC Frequency Divider Register (IICF) 13.3.2 IIC Frequency Divider Register (IICF) Figure 13-3. IIC Address Register (IICA) Table 13-2. IICA Field Descriptions Page Table 13-5. IIC Divider and Hold Values 13.3.3 IIC Control Register (IICC1) Figure 13-5. IIC Control Register (IICC1) Table 13-6. IICC1 Field Descriptions 13.3.4 IIC Status Register (IICS) Figure 13-6. IIC Status Register (IICS) Table 13-7. IICS Field Descriptions 13.3.5 IIC Data I/O Register (IICD) 13.3.6 IIC Control Register 2 (IICC2) 13.4 Functional Description 13.4.1 IIC Protocol 13.4.1.1 Start Signal 13.4.1.2 Slave Address Transmission 13.4.1.3 Data Transfer 13.4.1.4 Stop Signal 13.4.1.5 Repeated Start Signal 13.4.1.6 Arbitration Procedure 13.4.1.7 Clock Synchronization 13.4.1.8 Handshaking 13.4.1.9 Clock Stretching 13.4.2 10-bit Address 13.4.2.1 Master-Transmitter Addresses a Slave-Receiver 13.4.2.2 Master-Receiver Addresses a Slave-Transmitter 13.4.3 General Call Address 13.5 Resets 13.6 Interrupts 13.6.1 Byte Transfer Interrupt 13.6.2 Address Detect Interrupt 13.6.3 Arbitration Lost Interrupt Page 13.7 Initialization/Application Information Figure 13-11. IIC Module Quick Start Figure 13-12. Typical IIC Interrupt Routine 2-278 Freescale Semiconductor Page Page Chapter 14 Real-Time Counter (S08RTCV1) 14.1 Introduction 14.1.1 ADC Hardware Trigger 14.1.2 RTC Clock Sources 14.1.3 RTC Modes of Operation Page Chapter 14 Real-Time Counter (S08RTCV1) PORT A PORT G PORT F MCF51QE128 Block Diagram Highlighting RTC Block and Pins 14.1.6 Features 14.1.7 Modes of Operation 14.1.7.1 Wait Mode 14.1.7.2 Stop Modes 14.1.7.3 Active Background Mode 14.2 External Signal Description The RTC does not include any off-chip signals. 14.3 Register Definition Table 14-1. RTC Register Summary 14.3.1 RTC Status and Control Register (RTCSC) Figure 14-2. RTC Status and Control Register (RTCSC) Table 14-2. RTCSC Field Descriptions Table 14-3. RTC Prescaler Divide-by values 14.3.2 RTC Counter Register (RTCCNT) 14.3.3 RTC Modulo Register (RTCMOD) 14.4 Functional Description 14.4.1 RTC Operation Example 14.5 Initialization/Application Information Page Chapter 15 Serial Communications Interface (S08SCIV4) 15.1 Introduction 15.1.1 SCI Clock Gating 15.1.2 Interrupt Vectors Chapter 15 Serial Communications Interface (S08SCIV4) Figure 15-1. MCF51QE128 Series Block Diagram Highlighting SCI Block and Pins Figure 15-2. SCI Module Quick Start Page 15.1.3 Features 15.1.4 Modes of Operation 296 Freescale Semiconductor Get the latest version from freescale.com 15.1.5 Block Diagram Figure 15-3 shows the transmitter portion of the SCI. Figure 15-3. SCI Transmitter Block Diagram Internal Bus 1 Baud Rate Clock Figure 15-4 shows the receiver portion of the SCI. Figure 15-4. SCI Receiver Block Diagram 15.2 Register Definition 15.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) 15.2.2 SCI Control Register 1 (SCIxC1) This read/write register controls various optional features of the SCI system. Table 15-2. SCIxBDL Field Descriptions Figure 15-7. SCI Control Register 1 (SCIxC1) Table 15-3. SCIxC1 Field Descriptions 15.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. Figure 15-8. SCI Control Register 2 (SCIxC2) Table 15-4. SCIxC2 Field Descriptions Table 15-3. SCIxC1 Field Descriptions (continued) 15.2.4 SCI Status Register 1 (SCIxS1) Figure 15-9. SCI Status Register 1 (SCIxS1) Table 15-5. SCIxS1 Field Descriptions Table 15-4. SCIxC2 Field Descriptions (continued) Table 15-5. SCIxS1 Field Descriptions (continued) 15.2.5 SCI Status Register 2 (SCIxS2) This register contains one read-only status flag. Figure 15-10. SCI Status Register 2 (SCIxS2) Table 15-6. SCIxS2 Field Descriptions 15.2.6 SCI Control Register 3 (SCIxC3) Figure 15-11. SCI Control Register 3 (SCIxC3) Table 15-7. SCIxC3 Field Descriptions 15.2.7 SCI Data Register (SCIxD) 15.3 Functional Description 15.3.1 Baud Rate Generation 15.3.2 Transmitter Functional Description 15.3.2.1 Send Break and Queued Idle 15.3.3 Receiver Functional Description 15.3.3.1 Data Sampling Technique 15.3.3.2 Receiver Wakeup Operation 15.3.4 Interrupts and Status Flags 15.3.5 Additional SCI Functions 15.3.5.1 8- and 9-Bit Data Modes 15.3.5.2 Stop Mode Operation 15.3.5.3 Loop Mode 15.3.5.4 Single-Wire Operation Page Chapter 16 Serial Peripheral Interface (S08SPIV3) 16.1 Introduction 16.1.1 SPI Clock Gating 16.1.2 Interrupt Vector Chapter 16 Serial Peripheral Interface (S08SPIV3) Figure 16-1. MCF51QE128 Block Diagram Highlighting SPI Block and Pins Page Page 16.1.3 Features 16.1.4 Block Diagrams 16.1.4.1 SPI System Block Diagram 16.1.4.2 SPI Module Block Diagram Figure 16-3. SPI Module Block Diagram 16.1.5 SPI Baud Rate Generation 16.2 External Signal Description 16.2.1 SPSCK SPI Serial Clock 16.2.2 MOSI Master Data Out, Slave Data In 16.2.3 MISO Master Data In, Slave Data Out 16.2.4 SS Slave Select 16.3 Modes of Operation 16.3.1 SPI in Stop Modes 16.4 Register Definition 16.4.1 SPI Control Register 1 (SPIxC1) 16.4.2 SPI Control Register 2 (SPIxC2) Table16-2. SS Pin Function Table 16-1. SPIxC1 Field Descriptions (continued) 16.4.3 SPI Baud Rate Register (SPIxBR) Figure 16-7. SPI Baud Rate Register (SPIxBR) Figure 16-6. SPI Control Register 2 (SPIxC2) Table 16-3. SPIxC2 Register Field Descriptions 16.4.4 SPI Status Register (SPIxS) Table 16-4. SPIxBR Register Field Descriptions Figure 16-8. SPI Status Register (SPIxS) Table 16-5. SPIxS Register Field Descriptions 16.4.5 SPI Data Register (SPIxD) 16.5 Functional Description 16.5.1 SPI Clock Formats Page 16.5.2 SPI Interrupts 16.5.3 Mode Fault Detection Page Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) 17.1 Introduction Chapter 17 Timer/Pulse-Width Modulator (S08TPMV3) PORT A PORT G Figure 17-1. MCF51QE128 Series Block Diagram Highlighting TPM Block and Pins Page Page 17.1.4 Features 17.1.5 Modes of Operation 17.1.6 Block Diagram Timer/PWM Module (S08TPMV3) Figure 17-2. TPM Block Diagram Prescale and Select Clock Source Select 17.2 Signal Description 17.2.1 Detailed Signal Descriptions 17.2.1.1 EXTCLK External Clock Source 17.2.1.2 TPMxCHn TPM Channel n I/O Pin(s) Page Figure 17-6. Low-True Pulse of a Center-Aligned PWM 17.3 Register Definition This section consists of register descriptions in address order. 17.3.1 TPM Status and Control Register (TPMxSC) Figure 17-7. TPM Status and Control Register (TPMxSC) Table 17-2. TPMxSC Field Descriptions 17.3.2 TPM Counter Registers (TPMxCNTH:TPMxCNTL) Table 17-3. TPM-Clock-Source Selection Table17-4. Prescale Factor Selection Table17-2. TPMxSC Field Descriptions (continued) 17.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) 17.3.4 TPM Channel n Status and Control Register (TPMxCnSC) Table 17-5. TPMxCnSC Field Descriptions Table17-6. Mode, Edg e, and Level Selection 17.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) 17.4 Functional Description 17.4.1 Counter 17.4.1.1 Counter Clock Source 17.4.1.2 Counter Overflow and Modulo Reset 17.4.1.3 Counting Modes 17.4.1.4 Manual Counter Reset 17.4.2 Channel Mode Selection 17.4.2.1 Input Capture Mode 17.4.2.2 Output Compare Mode 17.4.2.3 Edge-Aligned PWM Mode 17.4.2.4 Center-Aligned PWM Mode 17.5 Reset Overview 17.5.1 General 17.5.2 Description of Reset Operation 17.6 Interrupts 17.6.1 General 17.6.2 Description of Interrupt Operation 17.6.2.1 Timer Overflow Interrupt (TOF) Description 17.6.2.2 Channel Event Interrupt Description Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG) 18.1 Introduction 18.1.1 Overview 18.1.2 Features 18.1.3 Modes of Operations Page 18.2 External Signal Descriptions 18.3 Memory Map/Register Definition 18.3.1 Configuration/Status Register (CSR) Figure 18-3. Configuration/Status Register (CSR) Table 18-5. CSR Field Descriptions Table18-5. CSR Field Descriptions (continued) 18.3.2 Extended Configuration/Status Register (XCSR) Figure 18-4. Extended Configuration/Status Register (XCSR) Table 18-7. XCSR Field Descriptions Table 18-7. XCSR Field Descriptions (continued) 18.3.3 Configuration/Status Register 2 (CSR2) Eqn. 18-1 Table18-8. CSR2 Reference Summary Table 18-7. XCSR Field Descriptions (continued) Figure 18-5. Configuration/Status Register 2 (CSR2) Table 18-9. CSR2 Field Descriptions Table 18-8. CSR2 Reference Summary (continued) Table 18-9. CSR2 Field Descriptions (continued) 18.3.4 Configuration/Status Register 3 (CSR3) Table 18-10. CSR3 Reference Summary Table 18-9. CSR2 Field Descriptions (continued) 18.3.5 BDM Address Attribute Register (BAAR) Figure 18-6. Configuration/Status Register 3 (CSR3) Table 18-11. CSR3 Field Descriptions 18.3.6 Address Attribute Trigger Register (AATR) Figure 18-7. BDM Address Attribute Register (BAAR) Table 18-12. BAAR Field Descriptions Figure 18-8. Address Attribute Trigger Register (AATR) Table 18-13. AATR Field Descriptions 18.3.7 Trigger Definition Register (TDR) Figure 18-9. Trigger Definition Register (TDR) Table 18-14. TDR Field Descriptions Table 18-14. TDR Field Descriptions (continued) 18.3.8 Program Counter Breakpoint/Mask Registers (PBR03, PBMR) Figure 18-10. Program Counter Breakpoint Register 0 (PBR0) Table 18-15. PBR0 Field Descriptions Figure 18-12. Program Counter Breakpoint Mask Register (PBMR) 18.3.9 Address Breakpoint Registers (ABLR, ABHR) 18.3.10 Data Breakpoint and Mask Registers (DBR, DBMR) Table 18-19. ABHR Field Description Figure 18-14. Data Breakpoint & Mask Registers (DBR, DBMR) Table 18-20. DBR Field Descriptions Table 18-21. DBMR Field Descriptions 18.3.11 Resulting Set of Possible Trigger Combinations 18.4 Functional Description 18.4.1 Background Debug Mode (BDM) 18.4.1.1 CPU Halt Table 18-23. CPU Halt Sources (continued) 18.4.1.2 Background Debug Serial Interface Controller (BDC) 18.4.1.3 BDM Communication Details Page Page Figure 18-17. BDM Target-to-Host Serial Bit Timing (Logic 0) 18.4.1.4 BDM Command Set Descriptions Figure 18-18. BDM Command Code Encodings Table 18-24. BDM Command Code Field Descriptions 18.4.1.5 BDM Command Set Summary Table 18-25. BDM Command Summary Table 18-25. BDM Command Summary (continued) Page Page Page Page Page Page Page 18.4.1.5.12 READ_PSTB Page Page 18.4.1.5.19 WRITE_DREG 18.4.1.5.21 WRITE_Rn 18.4.1.6 Serial Interface Hardware Handshake Protocol Page 18.4.1.7 Hardware Handshake Abort Procedure Page Page 18.4.2 Real-Time Debug Support 18.4.3 Real-Time Trace Support Page 18.4.3.1 Begin Execution of Taken Branch (PST = 0x05) Table 18-26. Processor Status Encodings (continued) Page 18.4.3.2 PST Trace Buffer (PSTB) 18.4.3.3 PST/DDATA Example 18.4.3.4 Processor Status, Debug Data Definition Page Page Page Page 18.4.4 Freescale-Recommended BDM Pinout Page Appendix A Revision History A.1 Changes between Rev. 2 and Rev. 3 Table 29. MCF51QE128RM Rev. 2 to Rev. 3 Changes Page Page How to Reach Us: