MCF51QE128 MCU Series Reference Manual, Rev. 3
190 Freescale Semiconductor
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Chapter 8 Interrupt Controller (CF1_INTC)
Figure 8-8. ISR Code Snippet with SWIACK
This snippet includes the prologue and epilogue for an interrupt service routine as well as code needed to
perform software IACK.
At the entry point (irqxx_entry), there is a two-instruction prologue to allocate space on the supervisor
stack to save the four volatile registers (d0, d1, a0, a1) defined in the ColdFire application binary interface.
After these registers have been saved, the ISR continues at the alternate entry point.
The software IACK is performed near the end of the ISR, after the source of the current interrupt request
has been negated. First, the appropriate memory-mapped byte location in the interrupt controller is read
(PC = 0x5C0). The CF1_INTC module returns the vector number of the highest priority pending request.
If no request is pending, zero is returned. The compare instruction is needed to manage a special case
involving pending level seven requests. Because the level seven requests are non-maskable, ISR is
interrupted to service one of these requests. To avoid any race conditions, this check ignores the two level
seven vector numbers (0x40, 0x41). The result is the conditional branch (PC = 0x5C8) is taken if there are
no pending requests or if the pending request is a level seven.
If there is a pending non-level seven request, execution continues with a three instruction sequence to
calculate and then branch to the appropriate alternate ISR entry point. This sequence assumes the
exception vector table is based at address 0x(00)00_0000 and that each ISR uses the same two-instruction
prologue shown here. The resulting alternate entry point is a fixed offset (8 bytes) from the normal entry
point defined in the exception vector table.
The ISR epilogue includes a three instruction sequence to restore the volatile registers from the stack and
return from the interrupt exception.
This example is intentionally simple, but does show how performing the software IACK and passing
control to an alternate entry point when there is a pending but masked interrupt request can avoid the
execution of the ISR epilogue, another interrupt exception, and the ISR prologue.
align 4
irqxx_entry:
00588: 4fef fff0 lea -16(sp),sp # allocate stack space
0058c: 48d7 0303 movem.l #0x0303,(sp) # save d0/d1/a0/a1 on stack
irqxx_alternate_entry:
00590:
.... irqxx_swiack:
005c0: 71b8 ffe0 mvz.b INTC_SWIACK.w,d0 # perform software IACK
005c4: 0c00 0041 cmpi.b #0x41,d0 # pending IRQ or level 7?
005c8: 6f0a ble.b irqxx_exit # no pending IRQ, then exit
005ca: 91c8 sub.l a0,a0 # clear a0
005cc: 2270 0c00 move.l 0(a0,d0.l*4),a1 # fetch pointer from xcpt table
005d0: 4ee9 0008 jmp 8(a1) # goto alternate isr entry point
align 4
irqxx_exit:
005d4: 4cd7 0303 movem.l (sp),#0x0303 # restore d0/d1/a0/a1
005d8: 4fef 0010 lea 16(sp),sp # deallocate stack space
005dc: 4e73 rte # return from handler