Freescale Semiconductor MCF51QE128RM manual Background / Mode Select BKGD/MS

Chapter 2 Pins and Connections

NOTE

The RESET pin does not contain a clamp diode to VDD and should not be driven above VDD.

NOTE

In EMC-sensitive applications, an external RC filter is recommended on the RESET pin, if enabled. See Figure 2-3for an example.

After a power-on reset (POR), the PTC4/RGPIO12/TPM3CH4/RSTO pin defaults to a general-purpose port pin, PTC4. Setting RSTOPE in SOPT1 configures the pin as an open drain with internal pullup acting as reset out (RSTO). The RSTO pin reflects the current state of the internal MCU reset signal. As long as the MCU is not in a reset state, the RSTO pin is driven high. When an internal reset occurs and RSTPE is set, the RSTO pin is pulled low for as long as the internal reset signal is low. This allows other devices in the system to detect the MCU’s reset state.

When enabled as the RSTO pin (RSTOPE = 1), the pin is automatically configured as an output only. The RSTO pin can be enabled independently of the RESET pin. After being configured as RSTO, the pin remains in this mode until the next POR.

NOTE

The RSTO pullup should not be used as a pullup for components external to the MCU. Inputs to internal gates connected to this pin are resistively pulled high, but VDD is not seen at the pin itself.

2.2.4Background / Mode Select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset (see the BDFR bit in Section 18.3.3, “Configuration/Status Register 2 (CSR2),” for more information), the PTA4/ACMP1O/BKGD/MS pin functions as a mode select pin. Immediately after any reset, the pin functions as the background data pin and can be used for background debug communication.

The debug communication function is enabled when SOPT1[BKGDPE] is set. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal pullup device is automatically enabled. BKGDPE is set following any reset of the MCU and must be cleared to use the PTA4/ACMP1O/BKGD/MS pin’s alternative pin functions.

If this pin is unconnected, the MCU enters normal operating mode at the rising edge of the internal reset after a POR or forced BDC reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a background debug force reset1, which forces the MCU to halt mode.

The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock can be as fast as the bus clock rate, so there should never be any significant capacitance connected to the BKGD/MS pin that could interfere with background serial communications.

1. Specifically, BKGD must be held low through the first 16 cycles after deassertion of the internal reset.

MCF51QE128 MCU Series Reference Manual, Rev. 3

38 Freescale Semiconductor

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