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Freescale Semiconductor MCF51QE128RM manual PSTBWA7, Pstb Valid Data Locations Oldest to Newest

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					Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
		Table 18-9. CSR2 Field Descriptions (continued)

Field					Description

22–21	PST trace buffer state. Indicates the current state of the PST trace buffer recording.
PSTBST	00 PSTB disabled
	01 PSTB enabled and waiting for the start condition
	10 PSTB enabled, recording and waiting for the stop condition
	11 PSTB enabled, completed recording after the stop condition was reached

20	Reserved, must be cleared.

19–16	Debug 1-pin hardware revision level. Indicates the hardware revision level of the 1-pin debug module implemented
D1HRL	in the ColdFire core. For this device, this field is 0x0.

15–8	PST trace buffer write address. Indicates the current write address of the PST trace buffer. The most-significant-bit
PSTBWA	of this field is sticky, that is, once set, it remains set until a PST/DDATA reset event occurs. As the ColdFire core
	inserts PST and DDATA packets into the trace buffer, this field is incremented. The value of the write address
	defines the next location in the PST trace buffer to be loaded. In other words, the contents of PSTB[PSTBWA-1]
	is the last valid entry in the trace buffer.
	The msb of this field can be used to determine if the entire PST trace buffer has been loaded with valid data.

			PSTBWA[7]		PSTB Valid Data Locations
			PSTBWA[7]		(Oldest to Newest)
					(Oldest to Newest)

			0		0, 1, ... PSTBWA-1

			1		PSTBWA, PSTBWA+1,..., 0, 1, PSTBWA-1

	The PSTBWA is unaffected when a buffer stop condition has been reached, the buffer is disabled, or a system
	reset occurs. This allows the contents of the PST trace buffer to be retrieved after these events to assist in debug.

7	PST trace buffer reset. Generates a reset of the PST trace buffer logic, which clears PSTBWA and PSTBST. The
PSTBR	same resources are reset whenever a disabled trace buffer becomes enabled and upon the receipt of a BDM GO
	command when operating in continuous trace mode. These reset events also clear any accumulation of PSTs.
	This bit always reads as a zero.
	0	Do not force a PST trace buffer reset
	1	Force a PST trace buffer reset

6	Automatic PC synchronization divide cycle counts by 16. This bit divides the cycle counts for automatic SYNC_PC
APCDIV16	command insertion by 16. See the APCSC and APCENB field descriptions.

5	Reserved, must be cleared.

MCF51QE128 MCU Series Reference Manual, Rev. 3

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Freescale Semiconductor MCF51QE128RM manual PSTBWA7, Pstb Valid Data Locations Oldest to Newest

Contents

MCF51QE64 MCF51QE32 Page MCF51QE128 Series Features Page MCF51QE128 Reference Manual MCF51QE128 MCU Series Reference Manual, Rev Contents Section Number Title Freescale Semiconductor Chapter Resets, Interrupts, and General System ControlTitle Chapter Parallel Input/Output Control 127 ColdFire Core Chapter Interrupt Controller CF1INTC Analog Comparator 3V ACMPVLPV1 11.1.5 Internal Clock Source S08ICSV3 Chapter Inter-Integrated Circuit S08IICV2 Section Number TitleReal-Time Counter S08RTCV1 Serial Peripheral Interface S08SPIV3 Chapter Timer/Pulse-Width Modulator S08TPMV3 Chapter Version 1 ColdFire Debug CF1DEBUG Appendix a Revision History Feature MCF51QE128 MCF51QE128 Series Features by MCU and PackageChapter Device Overview Devices in the MCF51QE128/64/32 SeriesXosc MCU Block DiagramMCF51QE128/64/32 Block Diagram System Clocks V1 ColdFire CoreInternal Clock Source ICS Module Module VersionsSystem Clock Distribution Simplified ICS Block DiagramIcsirclk ICS Modes of Operation FLL Bypassed Internal Low-Power FbilpFLL Engaged Internal FEI FLL Engaged External FEEStop Stop FLL Bypassed External Low-Power FbelpGet the latest version from freescale.com Get the latest version from freescale.com Device Pin Assignment Chapter Pins and ConnectionsPin Lqfp Pins in bold are added from the next smaller packageRecommended System Connections Basic System Connections Power Reset and RstoOscillator Background / Mode Select BKGD/MS General-Purpose I/O and Peripheral Ports ADC Reference Pins VREFH, VreflPin Pin Assignment by Package and Pin Sharing PriorityPriority Number Port Pin AltPort Pin Alt NumberGet the latest version from freescale.com Features Chapter Modes of OperationIntroduction Overview MCF51QE128/64/32 Power Modes Conceptual DrawingPMC CPU / Power Mode SelectionsStop3 Mode Regulator StateFull On Run Stop2 LPrunTransition # From Trigger Triggers for Transitions Shown in FigureSecure Mode Debug ModeLow-Power Run Mode LPrun Run ModeBDM in Low-Power Run Mode Run ModesLow-Power Wait Mode LPwait Wait ModeBDM in Low-Power Wait Mode Wait ModesStop2 Mode Stop3 Mode Stop4 Low Voltage Detect or BDM Enabled in Stop ModeLow-Range Oscillator Considerations for Stop2 Low-Power Mode Behavior On-Chip Peripheral Modules in Stop and Low-Power ModesAbbreviations used in Table CF1CORECOP BDCICS IRQGet the latest version from freescale.com Get the latest version from freescale.com MCF51QE128/64/32 Memory Map Chapter MemoryKbytes RAMRegister Addresses and Bit Assignments CPU Access Type Allowed by RegionRead Write Base Address Region Byte Long ByteColdFire Memory Organization Direct-Page Register Summary Sheet 1 Register Address Name Direct-Page Register Summary Sheet 2Direct-Page Register Summary Sheet 3 High-Page Register Summary Sheet 1 Direct-Page Register Summary Sheet 4High-Page Register Summary Sheet 2 High-Page Register Summary Sheet 3 High-Page Register Summary Sheet 4 High-Page Register Summary Sheet 5 Flash Module Reserved Memory LocationsReserved Flash Memory Addresses 0x0 0x1 0x2 0x30x0000040C 0x0 0x1 0x2 0x3 0x00000408Reserved Flash Memory Addresses Register NvprotColdFire Interrupt Controller Memory Map ColdFire Rapid Gpio Memory MapV1 ColdFire Rapid Gpio Memory Map V1 ColdFire Interrupt Controller Memory MapFlash RAMIntcsfrc IntccfrcFeatures Lov-Voltage Programming Sequence ExampleAddresses Desired Value Values Programmed Flash Clock Divider Register Fcdiv Register DescriptionsFlash Options Register Fopt and Nvopt Fcdiv Field Descriptions10. Fopt Field Descriptions Flash Configuration Register Fcnfg11. Fcnfg Field Descriptions Flash Protection Register Fprot and Nvprot12. Fprot Field Descriptions 13. Flash Protection Address Range0x40 0x00-0x3F0x41 0x00000-0x1EFFF 0x42Flash Status Register Fstat Command buffers are fullFcbef Fccf Fpviol Faccerr Fblank W1cFlash Command Register Fcmd Flash Command OperationsFunction Description 15. Fcmd Field Descriptions200 195 ⎟ 200 = 3% Writing the Fcdiv RegisterCommands Impossible Command Write SequenceStart ALL Program and EraseErase Verify Command Flash Commands16. Flash Command Description Fcmd NVMProgram Command 11. Example Program Command Flow Burst Program Command Command Buffer Empty Sector Erase CommandSequential Programming13. Example Sector Erase Command Flow 14. Example Mass Erase Command Flow Mass Erase CommandIllegal Flash Operations Flash Access ViolationsBackground Debug Mode Wait ModeOperating Modes Flash Protection ViolationsSecurity Unsecuring the MCU using Backdoor Key AccessFlash Reset Sequence ResetsReset While Flash Command Active Program and Erase TimesSecurity Set PRDIV8 and clock divider fields in CSR3 SyncStop Device is unsecureMicrocontroller Reset Chapter Resets, Interrupts, and General System ControlComputer Operating Properly COP Watchdog COP Configuration OptionsControl Bits Clock Source COP Overflow Count Copclks CoptIllegal Address Reset Illegal Operation ResetPin Configuration Options Interrupts and ExceptionsLow-Voltage Detect LVD System Power-On Reset OperationEdge and Level Sensitivity External Interrupt InitializationPeripheral Clock Gating LVD Reset OperationLVD Interrupt Operation Low-Voltage Warning LVW Interrupt OperationIrqsc Register Field Descriptions Interrupt Pin Request Status and Control Register IrqscIrqpdd Irqedg Irqpe Irqf Irqie Irqmod Irqack IrqpddPOR System Reset Status Register SRSPOR LVR System Options Register 1 SOPT1SOPT1 Register Field Descriptions System Options Register 2 SOPT2SOPT2 Register Field Descriptions System Device Identification Register SDIDH, SdidlSPI1PS SPSCLK1 MOSI1 MISO1 SS1 IIC1PS SDA1 SCL1Sdidh Register Field Descriptions Sdidl Register Field DescriptionsLvdf Lvdie LVDRE2 Lvdse LVDE2 Bgbe Lvdack LPR Lprs Lpwui Ppde Ppdc Ppdack SPMSC1 Register Field DescriptionsSPMSC2 Register Field Descriptions Lvwf Lvdv Lvwv Lvwie 11. LVD and LVW Trip Point Typical Values1Lvwf LvdvlvwvSystem Clock Gating Control 2 Register SCGC2 System Clock Gating Control 1 Register SCGC112. SCGC1 Register Field Descriptions TPM313. SCGC2 Register Field Descriptions RTC SPI2 SPI1FLS Freescale Semiconductor 109 110 Freescale Semiconductor Freescale Semiconductor 111 112 Freescale Semiconductor Chapter Parallel Input/Output Control Port Data and Data DirectionFreescale Semiconductor 113 Port Slew Rate Enable Port Internal Pull-up EnablePull-up, Slew Rate, and Drive Strength Data Direction Control Port Data Register Port ReadPort Data Set, Clear and Toggle Data Registers Port Drive Strength SelectFreescale Semiconductor 115 Keyboard Interrupts V1 ColdFire Rapid Gpio FunctionalityPort Data Set Registers Port Data Clear RegistersEdge and Level Sensitivity Edge Only SensitivityPull-up/Pull-down Resistors Freescale Semiconductor 117Parallel I/O, Keyboard Interrupt, and Pin Control Registers Pin Behavior in Stop ModesKeyboard Interrupt Initialization Port a RegistersPort a Data Register Ptad Port a Pull Enable Register PtapePort a Data Direction Register Ptadd PTAD7 PTAD6 PTAD5 PTAD41 PTAD3 PTAD2 PTAD1 PTAD0Port a Drive Strength Selection Register Ptads Port a Slew Rate Enable Register PtasePTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0Port B Data Register Ptbd Port B RegistersPort B Data Direction Register Ptbdd Ptads Register Field DescriptionsPort B Slew Rate Enable Register Ptbse Port B Pull Enable Register PtbpePtbdd Register Field Descriptions Ptbpe Register Field DescriptionsPort B Drive Strength Selection Register Ptbds Port C RegistersPort C Data Register Ptcd 10. Ptbds Register Field DescriptionsPort C Data Set Register Ptcset Port C Data Direction Register PtcddPort C Data Clear Register Ptcclr 12. Ptcdd Register Field DescriptionsPort C Toggle Register Ptctog Port C Pull Enable Register Ptcpe14. Ptcclr Register Field Descriptions 16. Ptcpe Register Field DescriptionsPort D Registers Port C Slew Rate Enable Register PtcsePort C Drive Strength Selection Register Ptcds Port D Data Register PtddPort D Data Direction Register Ptddd Port D Pull Enable Register Ptdpe19. Ptdd Register Field Descriptions 20. Ptddd Register Field DescriptionsPort E Registers Port D Slew Rate Enable Register PtdsePort D Drive Strength Selection Register Ptdds Port E Data Register PtedPort E Data Set Register Pteset Port E Data Direction Register Ptedd24. Pted Register Field Descriptions 25. Ptedd Register Field DescriptionsPort E Data Clear Register Pteclr Port E Pull Enable Register PtepePort E Toggle Register Ptetog PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0Port E Drive Strength Selection Register Pteds Port E Slew Rate Enable Register Ptese29. Ptepe Register Field Descriptions 30. Ptese Register Field DescriptionsPort F Registers Port F Pull Enable Register PtfpePort F Data Register Ptfd Port F Data Direction Register PtfddPort F Drive Strength Selection Register Ptfds Port F Slew Rate Enable Register Ptfse34. Ptfpe Register Field Descriptions 35. Ptfse Register Field DescriptionsPort G Data Register Ptgd Port G RegistersPort G Data Direction Register Ptgdd 36. Ptfds Register Field DescriptionsPort G Slew Rate Enable Register Ptgse Port G Pull Enable Register PtgpePort G Drive Strength Selection Register Ptgds 39. Ptgpe Register Field DescriptionsPort H Data Register Pthd Port H RegistersPort H Data Direction Register Pthdd 41. Ptgds Register Field DescriptionsPort H Slew Rate Enable Register Pthse Port H Pull Enable Register PthpePort H Drive Strength Selection Register Pthds 44. Pthpe Register Field DescriptionsPort J Registers Port J Data Register PtjdPort J Data Direction Register Ptjdd Port J Slew Rate Enable Register Ptjse Port J Pull Enable Register PtjpePort J Drive Strength Selection Register Ptjds 49. Ptjpe Register Field Descriptions10.1 KBI1 Interrupt Status and Control Register KBI1SC Keyboard Interrupt 1 KBI1 Registers51. Ptjds Register Field Descriptions 52. KBI1 Pin MappingKeyboard Interrupt 1 KBI2 Registers 10.2 KBI1 Interrupt Pin Select Register KBI1PE10.3 KBI1 Interrupt Edge Select Register KBI1ES 11.2 KBI2 Interrupt Pin Select Register KBI2PE 11.1 KBI2 Interrupt Status and Control Register KBI2SC57. KBI2SC Register Field Descriptions 58. KBI2PE Register Field Descriptions11.3 KBI2 Interrupt Edge Select Register KBI2ES 59. KBI2ES Register Field DescriptionsFreescale Semiconductor 143 144 Freescale Semiconductor Overview Chapter ColdFire CoreMemory Map/Register Description Supervisor Access Only Registers Supervisor/User Access RegistersData Registers D0-D7 ColdFire Core Programming ModelAddress Registers A0-A6 Supervisor/User Stack Pointers A7 and OTHERA7Data Freescale Semiconductor 149 Condition Code Register CCRProgram Counter PC Vector Base Register VBRCCR Field Descriptions CPU Configuration Register Cpucr Status Register SR SR Field DescriptionsBWD Instruction Set Architecture Isac Functional DescriptionInstruction Enhancements over Revision Isaa Instruction DescriptionException Processing Overview Exception Vector Assignments Vector StackedAssignment Numbers Offset Hex Counter Assignment Exception Stack Frame DefinitionNumbers Offset Hex Counter SSP →2.2 S08 and ColdFire Exception Processing Comparison Fault Status EncodingsFormat Field Encodings FS30 DefinitionException Processing Comparison Attribute S08 V1 ColdFireRTI RTE Address Error Exception Access Error ExceptionProcessor Exceptions Freescale Semiconductor 15910. ColdFire Opword Line Definition Illegal Instruction ExceptionLine OpMode Effective Address OpwordLine Instruction ClassPrivilege Violation Trace ExceptionFreescale Semiconductor 161 Unimplemented Line-A Opcode RTE and Format Error ExceptionUnimplemented Line-F Opcode Debug InterruptTrap Instruction Exception Fault-on-Fault HaltUnsupported Instruction Exception Interrupt ExceptionAccess User read-only BDM read-only Reset ExceptionBDM Load 0x60 D0 Store 0x40 D0 VER REV11. D0 Hardware Configuration Info Field Description 12. D1 Hardware Configuration Information Field Description FlashszSramsz Timing Assumptions Instruction Execution Timing13. Misaligned Operand References Address10 Size Bus Additional Operations CR/W14. Move Byte and Word Execution Times Move Instruction Execution Times15. Move Long Execution Times Source Destination Ax+ D16,Ax D8,Ax,Xi*SF Xxx.wlStandard One Operand Instruction Execution Times 16. One Operand Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl #xxx 17. Two Operand Instruction Execution Times Standard Two Operand Instruction Execution TimesMiscellaneous Instruction Execution Times 18. Miscellaneous Instruction Execution TimesOpcode Effective Address An+ D16,An D8,An,Xn*SF Xxx.wl #xxx Branch Instruction Execution Times 19. General Branch Instruction Execution Times20. Bcc Instruction Execution Times Chapter Interrupt Controller CF1INTC AttributeHCS08 Interrupt Controller CF1INTC V1 ColdFire Exception Vector Table 0x148 Next ACMPx 0x14C 0x134 Next SCI1rx 0x138 SCI1tx 0x13C IICx 0x140 KBIx 0x1440x150 Next SCI2rx 0x154 SCI2tx 0x158 0x180 NextInterrupt Source Number To V1 ColdFire coreFreescale Semiconductor 177 External Signal Description Memory Map and Register DefinitionModes of Operation Memory Map Intc Force Interrupt Register IntcfrcCF1INTC Memory Map Intcfrc Field Descriptions Intc Wake-up Control Register Intcwcr INTCPL6P7,6 Field DescriptionsFreescale Semiconductor 181 Intc Set Interrupt Force Register Intcsfrc Intcwcr Field DescriptionsENB Intcsfrc Field Descriptions Intc Clear Interrupt Force Register IntccfrcIntccfrc Field Descriptions Offset CF1INTCBASE + 0x1F IntccfrcVecn Swiack Intc Software and Level-nIACK Registers n = 1,2,3,...,7INTCSWIACK, INTCLVLnIACK Field Descriptions Interrupt Request Level and Priority Assignments10. Legend for Table Priority within Level Midpoint12. V1 ColdFire Interrupt Assignments TPM1ch0 TPM1ch1 TPM1ch2 TPM1ovflTPM2ch0 TPM2ch1 TPM2ch2 TPM2ovfl Handling of Non-Maskable Level 7 Interrupt Requests Initialization Information Application InformationEmulation of the HCS08’s 1-Level IRQ Handling Using INTCPL6P7,6 Registers More on Software IACKsFreescale Semiconductor 189 ISR Code Snippet with Swiack Freescale Semiconductor 191 192 Freescale Semiconductor Freescale Semiconductor 193 Chapter Rapid Gpio RgpioV1 ColdFire Core Freescale Semiconductor 195 Core IFPOEP Dsoc RAM RgpioModule RgpioPin Muxing + Pad Logic On-platform Bus RGPIODATA150Detailed Signal Descriptions Rgpio Module External I/O SignalsRgpio Detailed Signal Descriptions Memory Map/Register Definition Rgpio Write Memory MapRgpio Read Memory Map Rgpio Data Rgpiodata Rgpio Data Direction RgpiodirRgpiodir Field Descriptions DIRRgpio Clear Data Rgpioclr Rgpio Pin Enable RgpioenbRgpio Toggle Data Rgpiotog Rgpio Set Data RgpiosetRgpioclr Field Descriptions Rgpioset Field Descriptions10. Rgpiotog Field Descriptions Application 1 Simple Square-Wave GenerationTOG Field Description 15-0 Rgpio Toggle Data11. Square-Wave Output Performance SPI Speed @ Relative CPU f = 50 MHz 12. Emulated SPI Performance using Gpio Outputs29x Freescale Semiconductor 205206 Freescale Semiconductor ACMP/TPM Configuration Information Acmp Configuration InformationChapter Analog Comparator 3V ACMPVLPV1 Acmp Clock GatingInterrupt Vectors Freescale Semiconductor 209 210 Freescale Semiconductor Wait Mode Operation Block DiagramStop3 Mode Operation Stop2 Mode OperationStatus and Control Register ACMPxSC Register DefinitionAcbgs Acpe Acie ACF AC IRQ ACMP1 ACMP0 ACO ACMOD1 ACMOD2 SET ACFACMPxSC Field Descriptions InterruptsAcme Acmod214 Freescale Semiconductor Chapter Analog-to-Digital Converter S08ADC12V1 ADC Clock GatingFreescale Semiconductor 215 Analog-to-Digital Converter S08ADC12V1 Channel Assignments Module ConfigurationsAlternate Clock ADC Channel AssignmentHardware Trigger Temperature SensorFreescale Semiconductor 219 2provides a block diagram of the ADC moduleSignal Properties Name FunctionAD27-AD0 Analog Ground Vssad Analog Power VddadVoltage Reference High Vrefh Voltage Reference Low VreflCoco Input Channel SelectInput Select Data Result High Register Adcrh Status and Control Register 2 ADCSC2ADCSC2 Register Field Descriptions AdactCompare Value High Register Adccvh Data Result Low Register AdcrlADR10 ADR9 ADR8 ADCV11 ADCV10 ADCV9 ADCV8Compare Value Low Register Adccvl Configuration Register AdccfgAdccfg Register Field Descriptions AdlpcClock Divide Select Pin Control 1 Register APCTL1Conversion Modes Input Clock SelectPin Control 2 Register APCTL2 10. APCTL1 Register Field DescriptionsADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8 11. APCTL2 Register Field Descriptions Pin Control 3 Register APCTL3ADPC15 ADPC23ADPC21 12. APCTL3 Register Field DescriptionsADPC20 ADPC16Input Select and Pin Control Clock Select and Divide ControlHardware Trigger Conversion ControlCompleting Conversions Initiating ConversionsAborting Conversions Freescale Semiconductor 231Sample Time and Total Conversion Time Power Control13. Total Conversion Time vs. Control Conditions Adiclk AdlsmpAutomatic Compare Function MCU Wait Mode OperationMCU Stop2 Mode Operation MCU Stop3 Mode OperationStop3 Mode With Adack Disabled Stop3 Mode With Adack EnabledInitialization Sequence ADC Module Initialization ExamplePseudo-Code Example Freescale Semiconductor 235Reset Initialize ADC Adccfg = ADCSC2 = ADCSC1 = Check No External Pins and RoutingCOCO=1? Yes Read Adcrh Then Adcrl To Clear Coco Bit ContinueAnalog Reference Pins Analog Supply PinsAnalog Input Pins Freescale Semiconductor 237Sampling Error Sources of ErrorPin Leakage Error Noise-Induced ErrorsLinearity Errors Code Width and Quantization ErrorLsb = Freescale Semiconductor 239Code Jitter, Non-Monotonicity, and Missing Codes Freescale Semiconductor 241 242 Freescale Semiconductor Chapter Internal Clock Source S08ICSV3 Stop2 Mode ConsiderationsExternal Oscillator Freescale Semiconductor 243Internal Clock Source S08ICSV3 Freescale Semiconductor 245 246 Freescale Semiconductor Freescale Semiconductor 247 HGO, RANGE, EREFS, ERCLKEN, Erefsten2is the ICS block diagram FLL Bypassed External Low Power Fbelp FLL Bypassed Internal Low Power FbilpICS Register Summary Rdiv IrefsICSC1 Field Descriptions ICS Control Register 1 ICSC1Clks Rdiv Irefs Irclken Irefsten Reference Divide FactorICS Trim Register Icstrm ICS Control Register 2 ICSC2ICSC2 Field Descriptions Bdiv Range HGO Erefs Erclken ErefstenIcstrm Field Descriptions ICS Status and Control IcsscIcssc Field Descriptions DMX32 Irefst Clkst Oscinit FTRIM1 DRS512 16 20 MHz Reference range FLL factor DCO range608 19.92 MHz 1024 32 40 MHzFLL Engaged Internal FEI Operational ModesIREFS=1 CLKS=00 IREFS=0 IREFS=0 CLKS=10FLL Engaged External FEE FLL Bypassed Internal Low Power FbilpFLL Bypassed Internal FBI FLL Bypassed External FBEFLL Bypassed External Low Power Fbelp Mode SwitchingBus Frequency Divider StopDCO Maximum Frequency with 32.768 kHz Oscillator Low Power Bit UsageInternal Reference Clock External Reference ClockLocal Clock Fixed Frequency ClockChapter Inter-Integrated Circuit S08IICV2 Module ConfigurationIIC1 Position Options SOPT2IIC1PSMCF51QE128 Series Block Diagram Highlighting the IIC Modules Freescale Semiconductor 261 262 Freescale Semiconductor SCL Serial Clock Line SDA Serial Data LineFreescale Semiconductor 263 IIC Frequency Divider Register Iicf IIC Address Register IicaIica Field Descriptions = Unimplemented or ReservedHold Time Values for 8 MHz Bus Speed Iicf Field DescriptionsHold Times μs Mult ICR SDAICR SCL IIC Divider and Hold ValuesIICC1 Field Descriptions IIC Control Register IICC1IIC Status Register Iics Iics Field DescriptionsTCF IIC Control Register 2 IICC2 IIC Data I/O Register IicdIicd Field Descriptions Freescale Semiconductor 269IIC Protocol IICC2 Field DescriptionsGcaen Start Signal Slave Address TransmissionFreescale Semiconductor 271 Repeated Start Signal Stop SignalArbitration Procedure Data TransferHandshaking Clock SynchronizationClock Stretching Freescale Semiconductor 27313.4.2 10-bit Address Master-Transmitter Addresses a Slave-ReceiverMaster-Receiver Addresses a Slave-Transmitter General Call Address ResetsByte Transfer Interrupt Address Detect Interrupt276 Freescale Semiconductor Module Initialization Slave Initialization/Application InformationModule Initialization Master Module Use12. Typical IIC Interrupt Routine Freescale Semiconductor 279 280 Freescale Semiconductor ADC Hardware Trigger Chapter Real-Time Counter S08RTCV1RTC Clock Sources RTC Modes of OperationInterrupt Vector Freescale Semiconductor 283 MCF51QE128 Block Diagram Highlighting RTC Block and PinsActive Background Mode LPO RTC Register SummaryErclk IrclkRtcsc Field Descriptions RTC Status and Control Register RtcscRTC Prescaler Divide-by values RtifRTC Modulo Register Rtcmod RTC Counter Register RtccntRtccnt Field Descriptions Rtcmod Field DescriptionsPrescaler Period RTC Operation ExampleRtcps KHz Internal Clock MHz External Clock Rtclks =Rtccnt Rtif Internal 1-kHz Clock Source RTC Clock Rtcps =0x52 0x53 0x54 0x55 0x00 0x01 Freescale Semiconductor 289290 Freescale Semiconductor Chapter Serial Communications Interface S08SCIV4 SCI Clock GatingFreescale Semiconductor 291 Serial Communications Interface S08SCIV4 Module Initialization 294 Freescale Semiconductor Freescale Semiconductor 295 3shows the transmitter portion of the SCI Freescale Semiconductor 297 SCI Receiver Block DiagramSCI Baud Rate Registers SCIxBDH, SCIxBDL SCIxBDH Field DescriptionsLbkdie SCIxBDL Field Descriptions SCI Control Register 1 SCIxC1Loops Sciswai Rsrc Wake ILT LoopsSCI Control Register 2 SCIxC2 SCIxC2 Field DescriptionsTIE Tdre Rdrf Idle SCI Status Register 1 SCIxS1No parity error Framing errorParity error SCIxDSCIxS2 Field Descriptions SCI Status Register 2 SCIxS2Lbkdif Rxedgif Rxinv Rwuid BRK13 Lbkde RAF RXINV1SCIxC3 Field Descriptions SCI Control Register 3 SCIxC3Txdir TXINV1SCI Data Register SCIxD Baud Rate GenerationFreescale Semiconductor 305 Send Break and Queued Idle Transmitter Functional DescriptionData Sampling Technique Receiver Functional DescriptionBreak Character Length BRK13Idle-Line Wakeup Receiver Wakeup OperationFreescale Semiconductor 309 Interrupts and Status FlagsLoop Mode Stop Mode OperationAdditional SCI Functions 15.3.5.1 8- and 9-Bit Data ModesFreescale Semiconductor 311 Single-Wire Operation312 Freescale Semiconductor Chapter Serial Peripheral Interface S08SPIV3 SPI Clock GatingFreescale Semiconductor 313 MCF51QE128 Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor 315 316 Freescale Semiconductor Block Diagrams SPI System Block DiagramFreescale Semiconductor 317 SPI Module Block Diagram Freescale Semiconductor 319 SPI Baud Rate GenerationMosi Master Data Out, Slave Data Spsck SPI Serial ClockMiso Master Data In, Slave Data Out SS Slave SelectSPI in Stop Modes Modes of OperationSPI Control Register 1 SPIxC1 SPIxC1 Field DescriptionsSPI Control Register 2 SPIxC2 Master Mode Slave ModeSS Pin Function Modfen SsoeSPI Baud Rate Register SPIxBR SPI Stop in Wait ModeSPIxC2 Register Field Descriptions Modfen Bidiroe SpiswaiSPIxBR Register Field Descriptions SPI Status Register SPIxSSppr SPRSPI Data Register SPIxD SPI Clock Formats Freescale Semiconductor 327 10. SPI Clock Formats Cpha =11. SPI Clock Formats Cpha = SPI InterruptsFreescale Semiconductor 329 Mode Fault Detection330 Freescale Semiconductor Chapter Timer/Pulse-Width Modulator S08TPMV3 TPM Clock GatingFreescale Semiconductor 331 Timer/Pulse-Width Modulator S08TPMV3 Freescale Semiconductor 333 334 Freescale Semiconductor Freescale Semiconductor 335 336 Freescale Semiconductor Freescale Semiconductor 337 TPM Block DiagramExtclk Signal DescriptionTPMxCHn TPM Channel n I/O Pins Extclk External Clock SourceFreescale Semiconductor 339 High-True Pulse of an Edge-Aligned PWM TPMxSC Field Descriptions TPM Status and Control Register TPMxSCTOF Toie Cpwms Clksb Clksa PS2 PS1 TOFTPM-Clock-Source Selection TPM Counter Registers TPMxCNTHTPMxCNTLPrescale Factor Selection ClksbclksaTPMxCNT158 Any write to TPMxCNTH clears the 16-bit counter TPM Counter Modulo Registers TPMxMODHTPMxMODLTPMxCNT70 Any write to TPMxCNTL clears the 16-bit counter Freescale Semiconductor 343TPMxMOD158 TPM Channel n Status and Control Register TPMxCnSCTPMxMOD70 CHnF CHnIE MSnB MSnA ELSnB ELSnATPMxCnSC Field Descriptions MSnBMSnA ELSnBELSnA Mode ConfigurationMode, Edge, and Level Selection CpwmsMode, Edge, and Level Selection TPM Channel Value Registers TPMxCnVHTPMxCnVLTPMxCnV158 TPMxCnV70Counter Counter Clock SourceFreescale Semiconductor 347 TPM Clock Source Selection Counter Overflow and Modulo ResetManual Counter Reset Channel Mode SelectionInput Capture Mode Output Compare Mode15. PWM Period and Pulse Width ELSnA=0 Edge-Aligned PWM ModeFreescale Semiconductor 351 Center-Aligned PWM ModeReset Overview Description of Reset OperationGeneral Interrupt Local Source Description Enable Timer Overflow Interrupt TOF DescriptionDescription of Interrupt Operation Interrupt SummaryCenter-Aligned PWM Case Channel Event Interrupt DescriptionFreescale Semiconductor 355 Chapter Version 1 ColdFire Debug CF1DEBUGOEP Version 1 ColdFire Core CF1CorePST Bkgd BDCDebug Revision Summary Modes of OperationsRevision Csrhrl CSR2D1HRLCommand Type Flash BDM Command TypesCore Status Command Set BDM?External Signal Descriptions Debug Module Signals DescriptionBDM GO DRc Register Name Width Access Reset Value Section Bits Debug Module Memory MapCPU Configuration/Status Register CSR CSR Field Descriptions Bstat FOF TRG Halt Bkpt HRL BKD IPWTRC DDC UHE BTB NPL IPI SSM FID DDH TRC Extended Configuration/Status Register Xcsr Xcsr Reference SummaryMethod Reference Details Apcsc Apce CPU Cstat Halt Stop Eseqc Clksw SEC Erase EnbdmXcsr CPU StateEseqc W SEC RErase W CSR2 Reference Summary Configuration/Status Register 2 CSR2Xcsr CSR2 Syncpc IntervalCSR2 Field Descriptions Pstb Valid Data Locations Oldest to Newest PSTBWA710. CSR3 Reference Summary Configuration/Status Register 3 CSR3Pstbss Start Condition Stop ConditionBDM Address Attribute Register Baar BFC Bfcdiv DIV8BFCDIV8 SZM TTM TMM Address Attribute Trigger Register AatrBDM memory commands Normal processor access Else Reserved Signal of the processor’s local busTrigger Definition Register TDR SZML2EA L2EDL2T L1T L1EAL2T Three bits disables the address breakpoint Program Counter Breakpoint/Mask Registers PBR0-3, PbmrNo inversion Invert data breakpoint comparators 15. PBR0 Field Descriptions Mask ResetDRc 0x08 PBR0 DRc 0x09 Pbmr17. Pbmr Field Descriptions Address Breakpoint Registers ABLR, AbhrAbhr AblrData Breakpoint and Mask Registers DBR, Dbmr 19. Abhr Field Description21. Dbmr Field Descriptions 22. Access Size and Operand Data Location Background Debug Mode BDMAddress1 Access Size Operand Location Resulting Set of Possible Trigger Combinations23. CPU Halt Sources CPU HaltHalt Source Halt Timing Description Cpucrard =Cpucrird = Background Debug Serial Interface Controller BDC BDM Communication Details Freescale Semiconductor 385 15. BDC Host-to-Target Serial Bit Timing16. BDC Target-to-Host Serial Bit Timing Logic Freescale Semiconductor 387 BDM Command Set DescriptionsMemory Commands Miscellaneous CommandsCore Register Commands PST Trace Buffer Read CommandsCRG 24. BDM Command Code Field DescriptionsCRG CRN VBR25. BDM Command Summary BDM Command Set SummaryAckdisable AckenableReadcreg ReaddregReadpstb Writecreg SyncpcEnable host/target handshake protocol Always Available Disable host/target handshake protocol Always Available0x03 Freescale Semiconductor 3930x32 Host → Target Memory data7-0 Target → 0x36 Enter active background mode if enabled Non-intrusiveData7-0 0x3A MemoryXcsrsb 0x330x37 0x3BTarget 0x16 Memory Data15-8 Memory data7-0 0x12 Memory data7-00x12 Memory Target → Host 0x16 MemoryRead CPU control register Active Background No operation Non-intrusive0xA0+CRN Host → Target Dreg data Read debug control register Non-intrusive0x30 Address23-0 Target Memory data7-0 Target → Host0x35 0x310x39 0x50+CRN Host → Target Pstb dataRead Xcsr Status Byte Always Available Read general-purpose CPU register Active BackgroundRead CSR2 Status Byte Always Available Read CSR3 Status Byte Always AvailableWrite CPU control register Active Background Synchronize PC to PST/DDATA Signals Non-intrusive0xC0+CRN Creg data Freescale Semiconductor 4010x80+CRN Dreg data Write debug control register Non-intrusive0x10 Address23-0 Memory Data7-0 Host → targetWrite general-purpose CPU register Active Background Write Xcsr Status Byte Always Available Serial Interface Hardware Handshake ProtocolWrite CSR2 Status Byte Always Available Write CSR3 Status Byte Always AvailableFreescale Semiconductor 405 19. Target Acknowledge Pulse ACK20. Handshake Protocol at Command Level Hardware Handshake Abort ProcedureFreescale Semiconductor 407 21signal timing is not drawn to scale21. ACK Abort Procedure at the Command Level Real-Time Debug Support Real-Time Trace SupportFreescale Semiconductor 409 26. Processor Status Encodings Enter user modePST40 Definition Instructions, generate different encodingsBegin Execution of Taken Branch PST = 0x08-0x0BFreescale Semiconductor 411 PST Values Description 23. Example JMP Instruction Output in Pstb18.4.3.3 PST/DDATA Example PST Trace Buffer PstbPstbpst PstbddataProcessor Status, Debug Data Definition Instruction Operand Syntax 27. PST/DDATA Specification for User-Mode InstructionsPST/DDATA Freescale Semiconductor 415416 Freescale Semiconductor Freescale Semiconductor 417 Supervisor Instruction Set Freescale-Recommended BDM Pinout GND ResetNo Connect Freescale Semiconductor 419420 Freescale Semiconductor Changes between Rev and Rev Appendix a Revision HistoryMCF51QE128RM Rev to Rev Changes Chapter DescriptionRevision History Page How to Reach Us