Freescale Semiconductor MCF51QE128RM manual Section Number Title

Section Number		Title	Page
12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator			................................................257
12.4.6	Internal Reference Clock	................................................................................................	257
12.4.7	External Reference Clock	...............................................................................................	257
12.4.8 Fixed Frequency Clock			258

12.4.9The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source. ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid. Local Clock 258

Chapter 13

Inter-Integrated Circuit (S08IICV2)

13.1	Introduction			259
	13.1.1	Module Configuration		259
	13.1.2	Interrupt Vectors		259
	13.1.3	Features		262
	13.1.4 Modes of Operation			262
	13.1.5 Block Diagram			263
13.2	External Signal Description			263
	13.2.1 SCL — Serial Clock Line			263
	13.2.2 SDA — Serial Data Line			263
13.3	Register Definition			263
	13.3.1	IIC Address Register (IICA)		264
	13.3.2	IIC Frequency Divider Register (IICF)		264
	13.3.3	IIC Control Register (IICC1)		267
	13.3.4	IIC Status Register (IICS)		268
	13.3.5	IIC Data I/O Register (IICD)		269
	13.3.6	IIC Control Register 2 (IICC2)		269
13.4	Functional Description			270
	13.4.1	IIC Protocol		270
		13.4.1.1	Start Signal	271
		13.4.1.2	Slave Address Transmission	271
		13.4.1.3	Data Transfer	272
		13.4.1.4	Stop Signal	272
		13.4.1.5	Repeated Start Signal	272
		13.4.1.6	Arbitration Procedure	272
		13.4.1.7	Clock Synchronization	273
		13.4.1.8	Handshaking	273
		13.4.1.9	Clock Stretching	273
	13.4.2	10-bit Address		274
		13.4.2.1 Master-Transmitter Addresses a Slave-Receiver		274
		13.4.2.2 Master-Receiver Addresses a Slave-Transmitter		274
	13.4.3	General Call Address		275
13.5	Resets			275
			MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor				17
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