Freescale Semiconductor MCF51QE128RM manual Sdidh Register Field Descriptions

Chapter 5 Resets, Interrupts, and General System Control

R

W

Reset:

7	6	5	4	3	2	1	0
						ID[11:8]
—	—	—	—	1	1	0	0

	Figure 5-5. System Device Identification Register High (SDIDH)
	Table 5-6. SDIDH Register Field Descriptions
Field	Description
7–4	Reserved. Reading these bits results in an indeterminate value; writes have no effect.
Reserved
3–0	Part Identification Number. Each derivative in the ColdFire family has a unique identification number. The
ID[11:8]	MCF51QE128/64/32 are hard coded to the value 0xC15. See also ID bits in Table 5-7.

7 6 5 4

3 2 1 0

R

W

Reset:

ID[7:0]

0 0 0 1 0 1 0 1

	Figure 5-6. System Device Identification Register Low (SDIDL)
	Table 5-7. SDIDL Register Field Descriptions
Field	Description
7–0	Part Identification Number. Each derivative in the ColdFire family has a unique identification number. The
ID[7:0]	MCF51QE128/64/32 are hard coded to the value 0xC15. See also ID bits in Table 5-6.

5.7.6System Power Management Status and Control 1 Register (SPMSC1)

This high page register contains status and control bits to support the low voltage detect function, and it enables the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip voltage, see Table 5-10for the LVDV bit description in SPMSC3.

SPMSC1 is not reset when exiting from stop2.

R

W

Reset:

7	6	5	4	3	2	1	0
LVDF	0	LVDIE	LVDRE2	LVDSE	LVDE2	01	BGBE
	LVDACK
0	0	0	1	1	1	0	0

1Bit 1 is a reserved bit that must always be written to 0.

2This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-7. System Power Management Status and Control 1 Register (SPMSC1)

MCF51QE128 MCU Series Reference Manual, Rev. 3

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