Freescale Semiconductor MCF51QE128RM SCI Status Register 2 SCIxS2, SCIxS2 Field Descriptions

15.2.5SCI Status Register 2 (SCIxS2)

This register contains one read-only status flag.

R

W

Reset

7	6	5	4	3	2	1	0
LBKDIF	RXEDGIF	0	RXINV	RWUID	BRK13	LBKDE	RAF
0	0	0	0	0	0	0	0

		Figure 15-10. SCI Status Register 2 (SCIxS2)
		Table 15-6. SCIxS2 Field Descriptions
Field		Description
7	LIN Break Detect Interrupt Flag. LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
LBKDIF	character is detected. LBKDIF is cleared by writing a 1 to it.
	0	No LIN break character has been detected.
	1	LIN break character has been detected.
6	RxD Pin Active Edge Interrupt Flag. RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1)
RXEDGIF	on the RxD pin occurs. RXEDGIF is cleared by writing a 1 to it.
	0	No active edge on the receive pin has occurred.
	1	An active edge on the receive pin has occurred.
4	Receive Data Inversion. Setting this bit reverses the polarity of the received data input.
RXINV1	0	Receive data not inverted
	1	Receive data inverted
3	Receive Wake Up Idle Detect. RWUID controls whether the idle character that wakes up the receiver sets the
RWUID	IDLE bit.
	0	During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
	1	During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
2	Break Character Generation Length. BRK13 selects a longer transmitted break character length. Detection of a
BRK13	framing error is not affected by the state of this bit.
	0	Break character is transmitted with length of 10 bit times (11 if M = 1)
	1	Break character is transmitted with length of 13 bit times (14 if M = 1)
1	LIN Break Detection Enable. LBKDE selects a longer break character detection length. While LBKDE is set,
LBKDE	framing error (FE) and receive data register full (RDRF) flags are prevented from setting.
	0	Break character is detected at length of 10 bit times (11 if M = 1).
	1	Break character is detected at length of 11 bit times (12 if M = 1).
0	Receiver Active Flag. RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
RAF	cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
	SCI character is being received before instructing the MCU to go to stop mode.
	0	SCI receiver idle waiting for a start bit.
	1	SCI receiver active (RxD input not idle).

1Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.

When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave running 14% faster than the master. This would trigger normal break detection circuitry designed to detect a 10-bit break symbol. When the LBKDE bit is set,

MCF51QE128 MCU Series Reference Manual, Rev. 3

Freescale Semiconductor 303

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