AMD Am79C930 manual SD7-SD0, PTS3/OD2

P R E L I M I N A R Y

ISA PLUG AND PLAY PIN SUMMARY

No. of
Pins		Pin Name	Pin Function		Pin Style
7	LA23–LA17		ISA upper address bus lines		I
17	SA16–SA0		ISA lower address bus lines		I
8	SD7–SD0		ISA data bus lines		TS2
1			RESET input		I
	RESET
			Memory Read—used to ena ble the output drivers of the Am79C930 device for		I
1	MEMR
			ISA bus memory read accesses
			Memory Write—used to indicate that the current ISA bus cycle is a memory		I
1	MEMW
			write access
1	AEN		Address Enable—used to indicate that the current ISA bus I/O address is valid		I
1	BALE		Bus Address Latch Enable—used to indicate that the ISA address lines are		I
			valid
1	IOCHRDY		I/O Channel Ready—used to del ay the termination of the current ISA bus cycle		TS2
			I/O Read—this signal is asse rted by the ISA host system whenever an I/O read		I
1	IOR
			operation occurs
			I/O Write—this signal is asse rted by the ISA host system whenever an I/O write		I
1	IOW
			operation occurs
6	IRQ4, 5, 9, 10, 11, 12		Interrupt Request—this line is asse rted when the Am79C930 device needs		PTS3/OD2
			servicing from the software
1			Refresh—indicates that the current ISA bus cycle is a refresh operation		I
	RFRSH
1	PCMCIA		PCMCIA mode—selects PCMCIA or ISA Plug and Pl ay mode		I
1	PWRDWN		Powerdown—indicates that d evice is in the power down mode		TP1
			Memory Address Bus—these lines are used to address locations in the Flash
17	MA16–0		device, the SRAM device, and an extra peripheral device that are contained		TP1
			within an Am79C930-based design
8	MD7–0		Memory Data Bus—these lines are used to w rite and read data to/from Flash,		TS1
			SRAM, and/or an extra peripheral device within an Am79C930-based design
			Flash Chip Enable—this signal becomes asse rted when the Flash device has
1	FCE		been addressed by either the 80188 core of the Am79C930 device or by the		TP1
			software through the PCMCIA interface
			SRAM Chip Enable—this signal becomes asse rted when the SRAM device
1			has been addressed by either the 80188 core of the Am79C930 device or by		TP1
	SCE
			the software through the PCMCIA interface
			eXtra Chip Enable—this signal becomes asse rted when the extra peripheral
1			device has been addressed by the 80188 core of the Am79C930 device		TP1
	XCE			(XCE
			is not accessible through the system interface)
			Memory Output Enable—this signal becomes asse rted during reads of devices		TP1
1	MOE
			located on the memory interface bus
			Memory Write Enable—this signal becomes asse rted during writes to devices		TP1
1	MWE
			located on the memory interface bus
1	TCK		Test Clock—this is the clo ck signal for IEEE 1149.1 testing		I
1	TDI		Test Data In—this is the data input signal for IEEE 1149.1 testing		I
1	TDO		Test Data Out—this is the data output signal for IEEE 1149.1 testing		TS1
1	TMS		Test Mode Select—this is the test mode select for IEEE 1149.1 testing		I
1			Test Reset—this is the reset signal for IEEE 1149.1 testing		I
	TRST
			Test pin—when asse rted, this pin places the Am79C930 device into a		I
1	TEST
			non-IEEE 1149.1 test mode
1	CLKIN		Clock input to drive BIU, 80188 core, and TAI, supplying network data rate		I
			information
2	PMX1–2		Power Management Xtal—32-kHz Xtal input for sleep timer reference		I/XO
			Am79C930		23