
AMD | P R E L I M I N A R Y |
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TCR26: Reserved
This register is the TAI reserved location register.
CONFIGURATION REGISTER INDEX: | 1Ah | ||
Bit | Name | Reset Value | Description |
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Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | |
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| undefined data. |
TCR27: TIP LED Scramble
This register is the Network Interface Polarity register. This register is used to set the polarity of some of the transceiver interface output pins.
CONFIGURATION REGISTER INDEX: | 1Bh | |||
Bit | Name | Reset Value | Description | |
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7 | DISRNR | 0 | Disable RUNERR. When DISRNR is set to a 1, then the RUNERR | |
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| bit of TCR11 will always be held at a 0 value. When DISRNR is set | |
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| to a 0, then the RUNERR bit of TCR11 will function as described in | |
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| the TCR11 bit description. | |
6 | Reserved | – | Reserved. Must be written as a 0. Reads of these bits produce | |
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| undefined data. | |
5 | Reserved | 0 | Reserved. Must be written as a 0. Reads of these bits produce | |
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| undefined data. | |
4 | LNKDR | 0 | LNK pin drive. When set to a 0, the drive of the LNK pin will be open | |
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| drain. When set to a 1, the drive of the LNK pin will be totem pole, | |
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| i.e., both high and low output values will be driven. | |
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| Complete control of the function of the LNK pin is described in the | |
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3 | ACTDR | 0 | ACT pin drive. When set to a 0, the drive of the ACT pin will be open | |
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| drain. When set to a 1, the drive of the ACT pin will be totem pole, | |
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| i.e., both high and low output values will be driven. | |
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| Complete control of the function of the ACT pin is described in the | |
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2 | FDETPOL | 0 | FDET Polarity. When this bit is set to a 0, then the polarity of the | |
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| FDET output will be low assert, such that when the SFD pattern has | |
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| been recognized in the incoming receive data stream or the outgo- | |
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| ing transmit data stream, the FDET pin will be driven to a LOW logic | |
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| level. When this bit is set to a 1, then the polarity of the FDET output | |
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| will be high assert, such that when the SFD pattern has been recog- | |
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| nized in the incoming receive data stream or the outgoing transmit | |
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| data stream, the FDET pin will be driven to a HIGH logic level. | |
1 | TXPEPOL | 0 | TXPE Polarity. When this bit is set to a 0, then the polarity of the | |
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| TXPE output will be low assert, such that when the TGAP1 counter | |
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| expires, the TXPE pin will be driven to a LOW logic level. When this | |
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| bit is set to a 1, then the polarity of the TXPE output will be high as- | |
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| sert, such that when the TGAP1 counter expires, the TXPE pin will | |
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| be driven to a HIGH logic level. | |
0 | TXMODPOL | 0 | TXMOD Polarity. When this bit is set to a 0, then the polarity of the | |
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| TXMOD output will be low assert, such that when the TGAP2 | |
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| counter expires, the TXMOD pin will be driven to a LOW logic level. | |
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| When this bit is set to a 1, then the polarity of the TXMOD output will | |
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120 |
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| Am79C930 |