P R E L I M I N A R Y | AMD |
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LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RESET Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SWRESET (SIR0[7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CORESET (SIR0[6]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PCMCIA COR SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ISA PnP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SRES (TIR0[5]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
REGISTER DESCRIPTIONS | 75 |
System Interface Registers (SIR space) | 76 |
SIR0: General Configuration Register (GCR) | 77 |
SIR1: Bank Switching Select Register (BSS) | 78 |
SIR2: Local Memory Address Register [7:0] (LMA) | 79 |
SIR3: Local Memory Address Register [14:8] (LMA) | 79 |
SIR4: I/O Data Port A (IODPA) | 79 |
SIR5: I/O Data Port B (IODPB) | 80 |
SIR6: I/O Data Port C (IODPC) | 80 |
SIR7: I/O Data Port D (IODPD) | 80 |
MAC Interface Registers (MIR Space) | 80 |
MIR0: Processor Interface Register (PIR) | 80 |
MIR1: Power Up Clock Time [3:0] (PUCT) | 81 |
MIR2: Power Down Length Count [7:0] (PDLC) | 81 |
MIR3: Power Down Length Count [15:8] (PDLC) | 81 |
MIR4: Power Down Length Count [22:16] (PDLC) | 82 |
MIR5: Free Count [7:0] (FCNT) | 82 |
MIR6: Free Count [15:8] (FCNT) | 82 |
MIR7: Free Count [23:16] (FCNT) | 82 |
MIR8: Flash Wait States | 82 |
MIR9: TCR Mask STSCHG Data | 83 |
MIR10: Reserved | 85 |
MIR11: Reserved | 85 |
MIR12: Reserved | 85 |
MIR13: Reserved | 85 |
MIR14: Reserved | 85 |
MIR15: Reserved | 85 |
Transceiver Attachment Interface Registers (TIR Space) | 86 |
TIR0: Network Control | 89 |
TIR1: Network Status | 89 |
TIR2: Serial Device | 90 |
TIR3: Fast Serial Port Control | 91 |
TIR4: Interrupt Register 1 | 91 |
TIR5: Interrupt Register | 92 |
TIR6: Interrupt Unmask Register 1 | 93 |
TIR7: Interrupt Unmask Register 2 | 93 |
TIR8: Transmit Control | 94 |
TIR9: Transmit Status | 94 |
Am79C930 | 9 |
