Pcmcia I/O Read Access Timing Diagram

	P R E L I M I N A R Y	AMD
An
	tAVIGL	tIGHAX
REG
	tRGLIGL	tIGHRGH
CE
	tELIGL	tIGHEH
IORD	tIGLIGH
	tIGLIAL	tIGHIAH
INPACK
	tIGLWTL	tWTHQV
WAIT	tWTLWTH
	tIGLQV	tIGHQX
Do (Dout)	tIGQNZ
Do (Dout)
		tIGHQZ
		20138B-12

Figure 6. PCMCIA I/O READ Access Timing Diagram

An
tAVIWL	tIWHAX
REG
tRGLIWL	tIWHRGH
CE
tELIWL	tIWHEH
IOWR	tIWLIWH
tIWLWTL	tWTHIWH
WAIT	tWTLWTH
tDVIWL	tIWHDX
Di (Din)

	20138B-13
Figure 7. PCMCIA I/O WRITE Access Timing Diagram

Am79C930	149

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Image 149

AMD Am79C930 manual Pcmcia I/O Read Access Timing Diagram

Contents

Am79C930 Operating Conditions Optional ProcessingPackage Type Speed Jtag Trst TMS/T3 Reset PcmciaAdref Rxdata SIR0 MIR0 MIR1 SIR1 MIR15 SIR7 IreqSrdy INT1 TIR0 TCR0 IRQFifo TIR31 TCR31 MUX Table of Contents E L I M I N a R Y AMD TAP FSM TX FifoRX Fifo Register Descriptions TIR31 Test 126 Absolute Maximum Ratings AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Hfpe PTS1 Lfpe PTS1TP1, PTS1 Txpe TP1 Name Type Size of Pullup Size of Pulldown Name TypeLoad Ieee Sddata Reset LNK ACT CLK20 Test PwrdwnBale DRQ0 Txcmd Ieee Memr ISA Plug and Play Connection Diagram SD6 SD7SD5 SD2 SD4 SA1 SD5 Vsst ResetACT SDSEL2 ADIN1 TCK Adref PTS3/OD2 SD7-SD0 ISA Plug and Play PIN Summary Configuration Pins Pins with Internal Pull Up or Pull Down DevicesPIN Descriptions Pcmcia A14-0 Host System Interface PinsD7-0 Input/Output AEN ResetBale Iochrdy MD7-0 MA16-0IRQ4,5,9-12 Pwrdwn ClkinRxcin RXC Lfclk HfclkLlocke Rxdata Adref USER7Sdclk Sddata Avss TCKTDI VDD5 VDDU1 VSSVSSU1 VDDU2 Pin 2 USER3/SA16 Pin 1 USER2/LA19Pin 3 USER4/LA17 Pin 45 STSCHG/BALE Pin 92 USER7/IRQ11 Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 96 USER5/IRQ4/EXTCHBSY Pin 94 RXC/IRQ10/EXTA2DSTPin 95 USER6/IRQ5/EXTSDF Pin 100 LNK Pin 98 ACT Pin 102 Sddata Pin 101 SdclkPin 103 SDSEL3 Pin 105 SDSEL2 Pin 118 Lfpe Pin 115 TXCPin 120 Hfpe Pin 122 Rxpe Pin 129 Txpe Pin 126 TxcmdPin 131 Txmod Pin 132 Antslt Pin 144 LLOCKE/SA15 Pin 142 TXCMD/LA21Pin 143 TXDATA/LA20 Basic Functions Functional DescriptionDetailed Functions Bus Interface Unit E L I M I N a R Y AMD AMD E L I M I N a R Y Medium Allocation Memory InterfaceEmbedded AMD E L I M I N a R Y Bus Interface Unit Interaction Flash Memory ManagementTransceiver Attachment Interface Unit Management Transceiver Attachment Interface Unit TX Power Ramp Control Tbclk = Tsclk X Pin Timing Reference Name When RCEN=0 When RCEN=1 TX Status TX CRC GenerationStart of Frame Delimiter Detection RX Data Parallelization Rssi A/D Unit RX Status ReportingBit Ordering DC Bias Control Physical Header AccommodationBaud Determination Logic Adda Enext Ensar UXA2DST Clear Channel Assessment Logic Automatic Antenna Diversity Logic Current CCA result is reported in the Chbsy bit of TIR26Ubdcs Urssi Rssi = Rssi Ubdsd Urssi Stpen Ieee 1149.1 Test Access Port InterfaceTXC As Input Boundary Scan Circuit Power Down FunctionSupported Instructions Instruction Register and Decoding Logic E L I M I N a R Y AMD Am79C930 System Interface Resources Applicability to Ieee 802.11 Power Down ModesSoftware Access Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Resource Requirements Pcmcia Address Size Physical Memory Am79C930 Device Pcmcia Mode Common Memory Restricted SpaceSIR153 Description of Reserved Use XXX Am79C930 Device Pcmcia Mode Attribute Memory Map Pcmcia Address Attribute Memory Pcmcia Am79C930 Device Pcmcia Mode I/O MAPISA Plug and Play Mode Resources Kbytes of memory Am79C930 Device ISA Plug And Play Mode Memory MapMemory Range Memory Size ISA Address in Memory SIR153 Size of Space Physical Memory ISA Address Size Physical Memory AMD E L I M I N a R Y Physical Am79C930 Device ISA Plug And Play Mode I/O MAPISA SIR1 Resource Name Address Port Name ISA Ieee P996 I/O Address AccessWritedata Readdata Address ISA Plug and Play Plug and Play Port Register Name MAC Firmware Resources Physical Location of Memory Active Address Active Size Interrupt Channel Allocation in the 80188 CoreInterrupt Channel Interrupt Source INT0 TAI INT1 BIU Reset Pin Reset MethodsDMA Channel Allocation In The 80188 Core Loopback Operation Coreset SIR06 Sres TIR05 ISA PnP ResetRegister Descriptions System Interface Registers SIR space Bit Name Reset Value Description SIR0 General Configuration Register GCR SIR1 Bank Switching Select Register BSS MD70 during system interface accesses to Flash and Sram Bit Name Reset Value Description IODPA70SIR2 Local Memory Address Register 70 LMA SIR3 Local Memory Address Register 148 LMA MIR0 Processor Interface Register PIR MAC Interface Registers MIR SpaceSIR5 I/O Data Port B Iodpb MIR2 Power Down Length Count 70 Pdlc MIR1 Power Up Clock Time 30 Puct MIR4 Power Down Length Count 2216 Pdlc MIR3 Power Down Length Count 158 PdlcPermarest MIR5 Free Count 70 Fcnt Hostallow MIR8 Flash Wait StatesFLASHWAIT10 MIR9 TCR Mask Stschg Data Hostlongwait SRAMWAIT10Initdn Stschgd This register is reserved MIR10 ReservedReserved. Must be written as a 0. Reads of this bit produce Undefined data Transceiver Attachment Interface Registers TIR Space SIR110 ISA Plug Core TIRPlay TIR Register Name SIR110 Core TIR1 Network Status TIR0 Network Control TIR2 Serial Device TIR4 Interrupt Register TIR3 Fast Serial Port ControlChbsyc Antsw TIR5 Interrupt Register TIR7 Interrupt Unmask Register TIR6 Interrupt Unmask Register TIR8 Transmit Control Txcrc TIR9 Transmit StatusTxsdd Txbsy TIR11 Transmit Sequence Control TIR14 Byte Count Limit LSB TIR12 Byte Count Register LSBTIR13 Byte Count Register MSB TIR17 Receive Status Register TIR15 Byte Count Limit MSBTIR16 Receiver Control TIR18 RX Fifo Data Register RxbsyTIR19 Reserved TIR20 CRC32 Correct Byte Count LSB TIR23 CRC8 Correct Byte Count MSB TIR21 CRC32 Correct Byte Count MSBTIR22 CRC8 Correct Byte Count LSB Bit Name Reset Value Description CD70 TIR25 Configuration Data PortBy the current setting of the Configuration Index Register TIR24 TCR Index Register Srcs AddaStrtc TIR27 Serial Approximation Register TIR28 Rssi Lower Limit Bit Name Reset ValueTIR29 User Pin Data TIR30 Test Dummy Register These bit must be set to 0. Do not write to this register TAI Configuration Register Space TCRTCR0 Network Configuration Am79C930 105 TCR1 Transmit Configuration01h Bit Name Reset Value Description TCR3 Receive Configuration TCR2 Clock Recovery02h 03h 04h TCR4 Antenna Diversity TimerTCR5 TX Ramp Up Timing 05h 06h TCR6 TX Ramp Down TimingTCR7 Pin Data a 07h Txcmdt U1INTCNTAntsltld Txdatald Bit Name Reset Value Description SDLT158 00h Bit Name Reset Value Description SDLT70 00hTCR8 Start Delimiter LSB 08h 0Bh TCR11 Interrupt RegisterTCR12 Interrupt Unmask Register 0Ch TCR14 Pin Configuration B TCR13 Pin Configuration a0Dh 0Eh Am79C930 113 TCR15 Pin Configuration C0Fh Stschgfn ActenTCR16 Baud Detect Start 10h 12h Bit Name Reset Value Description 11h Bit Name Reset Value DescriptionUndefined data BDLLT50 TCR18 Baud Detect Upper Limit 13h TCR19 Baud Detect Accept Count for Carrier SenseBDCS50 TCR20 Baud Detect Accept Count for Stop Diversity TCR22 Baud Detect Accept Count 15h Bit Name Reset Value Description BDRN3016h TCR23 Baud Detect Fail Count 18h TCR25 Rssi ConfigurationSS50 00h 19h CACT=TIR277 Analog-to-Digital State Machine Timing Am79C930 119 1Bh TCR26 Reserved1Ah Am79C930 121 TCR28 Clear Channel Assessment Configuration1Ch Bit Name Reset Value Description 1Eh TCR29 Reserved1Dh Am79C930 123 TCR31 Device Revision1Fh Description Sreset Pcmcia Configuration Option RegisterPcmcia Card Configuration and Status Register Pcmcia CCR Registers and Pcmcia CIS Space Til the interrupt has been serviced not pulse generated Vice actually enters the power down mode InterruptPcmcia Card Information Structure CIS Am79C930 125 Am79C930 DC Characteristics DC CharacteristicsAbsolute Maximum Ratings Operating Ranges Commercial C Devices Parameter Description Test Conditions Min Max DC Characteristics Am79C930 DC CharacteristicsAm79C930 127 Absolute Maximum Ratings Temperature TA C to + 70C Supply VoltagesVDDP, VDD5 To 3.6 Am79C930 129 130 Ieee 1149.1 DC Characteristics 5.0 and 3.3 Unit Pcmcia Memory Read AccessAm79C930 131 132 Pcmcia Memory Write Access Am79C930 133 Pcmcia I/O Read Access 134 Pcmcia I/O Write Access Am79C930 135 136 ISA Access Am79C930 137 Memory BUS Read Access 138 Memory BUS Write Access Am79C930 139 140 Am79C930 141 AC Characteristics TAI Interface Absolute Maximum Ratings 142 TAI Interface AC CharacteristicsMax Unit Am79C930 143 144 Am79C930 145 146 Clkin ↓ TCK − ANALOG-TO-DIGITAL A/D Converter CharacteristicsAm79C930 147 Pcmcia Bus Interface Waveforms Timing WaveformsREG Din Pcmcia I/O Read Access Timing Diagram 150 ISA Bus Interface Waveforms Clkin Clkout Memory Bus Interface Waveforms 152 Clock Waveforms RCO TAI WaveformsICO 154 Programmable Interface Waveforms TDI, TMS Ieee 1149.1 Interface WaveformsAm79C930 155 156 AC Test Reference WaveformsPcmcia AC Test Reference Waveform V Non-PCMCIA AC Test Reference Waveform NON-PCMCIA AC Test Reference Waveform 158 Physical DimensionsPQT144 Pin Thin Quad Flat Pack measured in millimeters Typical Am79C930 System Application Device Configuration Frame Reception Frame Transmission Trademarks

P R E L I M I N A R Y

Figure 6. PCMCIA I/O READ Access Timing Diagram

Di (Din)

Figure 7. PCMCIA I/O WRITE Access Timing Diagram

Am79C930

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