
AMD | P R E L I M I N A R Y |
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TIR8: Transmit Control
This register is the Transmitter Control register.
Bit | Name | Reset Value |
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7 | TXRES | 0 |
| Transmit Reset. When this bit is set to 1, the internal Transmit Re- | |||
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| set signal is asserted. When this bit is set to 0, the internal Transmit | |||
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| Reset signal is deasserted. The transmit FIFO is NOT reset | |||
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| by TXRES. |
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6 | TXFR | 0 |
| Transmit FIFO Reset. When this bit is set to 1, the internal Transmit | |||
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| FIFO Reset signal is asserted. When this bit is set to 0, the internal | |||
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| Transmit FIFO Reset signal is deasserted. | |||
5 | DMA_SEL | 0 |
| DMA Select. When this bit is set to 1, the TXFIFO Not_Full signal is | |||
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| routed to both of the 80188 DMA channels. When this bit is set to 0, | |||
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| the TXFIFO Not_Full signal is routed to only DMA channel 1 of | |||
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| the 80188. |
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4 | EN_TX_CRC | 0 |
| Enable | |||
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| itiation of a transmission will commence when the logical AND of | |||
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| the TXS bit (TIR8, bit 0) and the CRC32_GOOD output of the | |||
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| CRC32 block becomes TRUE. Typically, the EN_TX_CRC bit and | |||
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| the TXS bit are set together during a reception, such that if the re- | |||
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| ception concludes with a correct CRC32 indication, then the trans- | |||
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| mit state machine will automatically be started. When this bit is set | |||
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| to 0, initiation of transmission will commence solely on the basis of | |||
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| the setting of the TXS bit (TIR8, bit 0). | |||
3 | RATE_SW | – | Rate Switch. When this bit is set to 1, the rate of data transmission | ||||
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| will automatically change immediately following the transmission of | |||
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| the last bit of the PFLth byte that follows the last bit of the Start of | |||
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| Frame Delimiter, where PFL is defined in TCR3, bits [3:0}. Since | |||
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| the PFL field of TCR3 is typically used to demark the PHY HEADER | |||
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| from the MAC data (and hence, it is used to determine the starting | |||
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| point for MAC CRC32 calculation), the rate switch will typically oc- | |||
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| cur on the PHY/MAC boundary. The rate of transmission will | |||
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| change from DR to DR XOR 0x1, where DR is the Data Rate field as | |||
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| defined in TCR30, bits [2:0}. When this bit is set to 0, no rate switch | |||
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| will occur. RX operations are unaffected by this bit. For rate switch- | |||
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| ing on the RX side, an external decode to RX clock and TX data is | |||
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| typically performed. |
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TCRC[1:0] | 00b | Transmit CRC type. These two bits are used to determine the na- | |||||
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| ture of the CRC field that is appended to the current frame. These | |||
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| bits must be stable throughout any given transmission. The follow- | |||
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| ing interpretations have been assigned to these bits: | |||
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| TCRC[1:0] | Transmitted CRC |
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| 00 | No CRC is appended |
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| 01 | CRC8 is appended |
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| 10 | CRC32 is appended |
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| 11 | No CRC is appended |
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0 | TXS | 0 |
| Transmit Start. |
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| When this bit is set to 1, then the transmit state machine begins op- | |||
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| eration. The transmit state machine is | |||
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| bit must be reset to 0 and set again to 1 before a subsequent trans- | |||
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| mission will begin. The transmit busy bit will be set in the transmit | |||
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| status register (TIR9) to indicate the state of transmit. Resetting this | |||
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| bit to 0 during transmission will not cause the current transmission | |||
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| to be aborted. Transmission abort is performed with the TXRES bit. | |||
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94 |
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| Am79C930 |
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