TCR4 Antenna Diversity Timer, 04h, 05h, Am79C930 107 | AMD specification

P R E L I M I N A R Y	AMD

to delay the start of CRC8 and CRC32 and DC bias control calculation for both receive and transmit frames. The physical header field is assumed to begin after the Start of Frame Delimiter has been detected.

TCR4: Antenna Diversity Timer

This register is the Antenna Diversity Timer register used to control antenna dwell time during antenna diversity measurements.

CONFIGURATION REGISTER INDEX:			04h
Bit	Name	Reset Value	Description

7	ANTEN	0	Antenna Diversity Enable. When set to a 1, the internal antenna di-
			versity logic is used to select the antenna. When set to a 0, software
			has control over antenna selection through the ANTS bit of
			TIR26[4] and the ANTSLTLD bit of TCR7[1]. Dwell times for an-
			tenna measurements are still used to obtain RSSI data when this bit
			is set to 0, but final antenna selection will be controlled by software.
6	Reserved	–	Reserved. Must be written as a 0. Reads of this bit produce
			undefined data.
5–0	ADT[5:0]	00h	Antenna Diversity Timer. Dwell time per antenna in time steps of
			CLKIN period times 20 when the CLKGT20 bit of MIR9 is set to 0,
			and time steps of CLKIN period times 40, when the CLKGT20 bit of
			MIR9 is set to 1. When the value in this register is “00,” then the di-
			versity switching function is disabled.

TCR5: TX Ramp Up Timing

This register is the TX Ramp Up Timing register. This register determines the ramp up timing of the TX enable signals.

CONFIGURATION REGISTER INDEX:			05h
Bit	Name	Reset Value	Description

7:4	TGAP1[3:0]	0h	Transmit Timing Gap 1. These bits are used to determine the gap
			between the assertion of the T1 signal and the assertion of the T2
			signal. T1 and T2 can be used to control the timing of the TXCMD
			and TXPE pins, respectively. The interval is programmable with a
			resolution equal to 20 times the CLKIN period when the CLKGT20
			bit of MIR9 is set to 0 and a resolution equal to 40 times the CLKIN
			period when the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data
			rate with CLKIN = 20MHz and CLKGT20 = 0, the resolution is 1 μ.
3:0	TGAP2[3:0]	0h	Transmit Timing Gap 2. These bits are used to determine the gap
			between the assertion of the T2 signal and the assertion of the T3
			signal. The interval is programmable with a resolution equal to 20
			times the CLKIN period when the CLKGT20 bit of MIR9 is set to 0

and a resolution equal to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 μ.

Am79C930

107

Image 107

AMD manual TCR4 Antenna Diversity Timer, 04h, TCR5 TX Ramp Up Timing, 05h, Am79C930 107

Contents

Am79C930 Speed Optional ProcessingOperating Conditions Package Type Rxdata Reset PcmciaJtag Trst TMS/T3 Adref INT1 IreqSIR0 MIR0 MIR1 SIR1 MIR15 SIR7 Srdy MUX IRQTIR0 TCR0 Fifo TIR31 TCR31 Table of Contents E L I M I N a R Y AMD TAP FSM TX FifoRX Fifo Register Descriptions TIR31 Test 126 Absolute Maximum Ratings AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Txpe TP1 Lfpe PTS1Hfpe PTS1 TP1, PTS1 Name Type Size of Pullup Size of Pulldown Name TypeLoad DRQ0 Txcmd Ieee Memr Reset LNK ACT CLK20 Test PwrdwnIeee Sddata Bale ISA Plug and Play Connection Diagram SD2 SD4 SD7SD6 SD5 TCK Adref SD5 Vsst ResetSA1 ACT SDSEL2 ADIN1 PTS3/OD2 SD7-SD0 ISA Plug and Play PIN Summary Pcmcia Pins with Internal Pull Up or Pull Down DevicesConfiguration Pins PIN Descriptions Input/Output Host System Interface PinsA14-0 D7-0 Iochrdy ResetAEN Bale MD7-0 MA16-0IRQ4,5,9-12 RXC ClkinPwrdwn Rxcin Rxdata HfclkLfclk Llocke Sddata USER7Adref Sdclk VDD5 TCKAvss TDI VDDU2 VSSVDDU1 VSSU1 Pin 45 STSCHG/BALE Pin 1 USER2/LA19Pin 2 USER3/SA16 Pin 3 USER4/LA17 Pin 92 USER7/IRQ11 Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 96 USER5/IRQ4/EXTCHBSY Pin 94 RXC/IRQ10/EXTA2DSTPin 95 USER6/IRQ5/EXTSDF Pin 100 LNK Pin 98 ACT Pin 105 SDSEL2 Pin 101 SdclkPin 102 Sddata Pin 103 SDSEL3 Pin 122 Rxpe Pin 115 TXCPin 118 Lfpe Pin 120 Hfpe Pin 132 Antslt Pin 126 TxcmdPin 129 Txpe Pin 131 Txmod Pin 144 LLOCKE/SA15 Pin 142 TXCMD/LA21Pin 143 TXDATA/LA20 Bus Interface Unit Functional DescriptionBasic Functions Detailed Functions E L I M I N a R Y AMD AMD E L I M I N a R Y Medium Allocation Memory InterfaceEmbedded AMD E L I M I N a R Y Bus Interface Unit Interaction Flash Memory ManagementTransceiver Attachment Interface Unit Management Transceiver Attachment Interface Unit TX Power Ramp Control Tbclk = Tsclk X Pin Timing Reference Name When RCEN=0 When RCEN=1 RX Data Parallelization TX CRC GenerationTX Status Start of Frame Delimiter Detection Rssi A/D Unit RX Status ReportingBit Ordering Adda Enext Ensar UXA2DST Physical Header AccommodationDC Bias Control Baud Determination Logic Clear Channel Assessment Logic Rssi = Rssi Current CCA result is reported in the Chbsy bit of TIR26Automatic Antenna Diversity Logic Ubdcs Urssi Ubdsd Urssi Stpen Ieee 1149.1 Test Access Port InterfaceTXC As Input Instruction Register and Decoding Logic Power Down FunctionBoundary Scan Circuit Supported Instructions E L I M I N a R Y AMD Am79C930 System Interface Resources Applicability to Ieee 802.11 Power Down ModesSoftware Access Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Resource Requirements Description of Reserved Use Am79C930 Device Pcmcia Mode Common Memory Restricted SpacePcmcia Address Size Physical Memory SIR153 XXX Am79C930 Device Pcmcia Mode Attribute Memory Map Pcmcia Address Attribute Memory Pcmcia Am79C930 Device Pcmcia Mode I/O MAPISA Plug and Play Mode Resources ISA Address in Memory SIR153 Size of Space Physical Memory Am79C930 Device ISA Plug And Play Mode Memory MapKbytes of memory Memory Range Memory Size ISA Address Size Physical Memory AMD E L I M I N a R Y Resource Name Am79C930 Device ISA Plug And Play Mode I/O MAPPhysical ISA SIR1 Readdata Port Name ISA Ieee P996 I/O Address AccessAddress Writedata Address ISA Plug and Play Plug and Play Port Register Name MAC Firmware Resources Physical Location of Memory Active INT0 TAI INT1 BIU Interrupt Channel Allocation in the 80188 CoreAddress Active Size Interrupt Channel Interrupt Source Loopback Operation Reset MethodsReset Pin DMA Channel Allocation In The 80188 Core Coreset SIR06 Sres TIR05 ISA PnP ResetRegister Descriptions System Interface Registers SIR space Bit Name Reset Value Description SIR0 General Configuration Register GCR SIR1 Bank Switching Select Register BSS SIR3 Local Memory Address Register 148 LMA Bit Name Reset Value Description IODPA70MD70 during system interface accesses to Flash and Sram SIR2 Local Memory Address Register 70 LMA MIR0 Processor Interface Register PIR MAC Interface Registers MIR SpaceSIR5 I/O Data Port B Iodpb MIR2 Power Down Length Count 70 Pdlc MIR1 Power Up Clock Time 30 Puct MIR5 Free Count 70 Fcnt MIR3 Power Down Length Count 158 PdlcMIR4 Power Down Length Count 2216 Pdlc Permarest MIR9 TCR Mask Stschg Data MIR8 Flash Wait StatesHostallow FLASHWAIT10 Stschgd SRAMWAIT10Hostlongwait Initdn Undefined data MIR10 ReservedThis register is reserved Reserved. Must be written as a 0. Reads of this bit produce Transceiver Attachment Interface Registers TIR Space TIR Register Name TIRSIR110 ISA Plug Core Play SIR110 Core TIR1 Network Status TIR0 Network Control TIR2 Serial Device Antsw TIR3 Fast Serial Port ControlTIR4 Interrupt Register Chbsyc TIR5 Interrupt Register TIR7 Interrupt Unmask Register TIR6 Interrupt Unmask Register TIR8 Transmit Control Txbsy TIR9 Transmit StatusTxcrc Txsdd TIR11 Transmit Sequence Control TIR14 Byte Count Limit LSB TIR12 Byte Count Register LSBTIR13 Byte Count Register MSB TIR17 Receive Status Register TIR15 Byte Count Limit MSBTIR16 Receiver Control TIR20 CRC32 Correct Byte Count LSB RxbsyTIR18 RX Fifo Data Register TIR19 Reserved TIR23 CRC8 Correct Byte Count MSB TIR21 CRC32 Correct Byte Count MSBTIR22 CRC8 Correct Byte Count LSB TIR24 TCR Index Register TIR25 Configuration Data PortBit Name Reset Value Description CD70 By the current setting of the Configuration Index Register TIR27 Serial Approximation Register AddaSrcs Strtc TIR30 Test Dummy Register Bit Name Reset ValueTIR28 Rssi Lower Limit TIR29 User Pin Data These bit must be set to 0. Do not write to this register TAI Configuration Register Space TCRTCR0 Network Configuration Am79C930 105 TCR1 Transmit Configuration01h Bit Name Reset Value Description 03h TCR2 Clock RecoveryTCR3 Receive Configuration 02h 05h TCR4 Antenna Diversity Timer04h TCR5 TX Ramp Up Timing 07h TCR6 TX Ramp Down Timing06h TCR7 Pin Data a Txdatald U1INTCNTTxcmdt Antsltld 08h Bit Name Reset Value Description SDLT70 00hBit Name Reset Value Description SDLT158 00h TCR8 Start Delimiter LSB 0Ch TCR11 Interrupt Register0Bh TCR12 Interrupt Unmask Register 0Eh TCR13 Pin Configuration aTCR14 Pin Configuration B 0Dh Am79C930 113 TCR15 Pin Configuration C0Fh 10h ActenStschgfn TCR16 Baud Detect Start TCR18 Baud Detect Upper Limit 11h Bit Name Reset Value Description12h Bit Name Reset Value Description Undefined data BDLLT50 TCR20 Baud Detect Accept Count for Stop Diversity TCR19 Baud Detect Accept Count for Carrier Sense13h BDCS50 TCR23 Baud Detect Fail Count 15h Bit Name Reset Value Description BDRN30TCR22 Baud Detect Accept Count 16h 19h TCR25 Rssi Configuration18h SS50 00h CACT=TIR277 Analog-to-Digital State Machine Timing Am79C930 119 1Bh TCR26 Reserved1Ah Am79C930 121 TCR28 Clear Channel Assessment Configuration1Ch Bit Name Reset Value Description 1Eh TCR29 Reserved1Dh Am79C930 123 TCR31 Device Revision1Fh Description Pcmcia CCR Registers and Pcmcia CIS Space Pcmcia Configuration Option RegisterSreset Pcmcia Card Configuration and Status Register Am79C930 125 Vice actually enters the power down mode InterruptTil the interrupt has been serviced not pulse generated Pcmcia Card Information Structure CIS Commercial C Devices DC CharacteristicsAm79C930 DC Characteristics Absolute Maximum Ratings Operating Ranges Parameter Description Test Conditions Min Max DC Characteristics Am79C930 DC CharacteristicsAm79C930 127 To 3.6 Temperature TA C to + 70C Supply VoltagesAbsolute Maximum Ratings VDDP, VDD5 Am79C930 129 130 Ieee 1149.1 DC Characteristics 5.0 and 3.3 Unit Pcmcia Memory Read AccessAm79C930 131 132 Pcmcia Memory Write Access Am79C930 133 Pcmcia I/O Read Access 134 Pcmcia I/O Write Access Am79C930 135 136 ISA Access Am79C930 137 Memory BUS Read Access 138 Memory BUS Write Access Am79C930 139 140 Am79C930 141 AC Characteristics TAI Interface Absolute Maximum Ratings 142 TAI Interface AC CharacteristicsMax Unit Am79C930 143 144 Am79C930 145 146 Clkin ↓ TCK − ANALOG-TO-DIGITAL A/D Converter CharacteristicsAm79C930 147 Din Timing WaveformsPcmcia Bus Interface Waveforms REG Pcmcia I/O Read Access Timing Diagram 150 ISA Bus Interface Waveforms Clkin Clkout Memory Bus Interface Waveforms 152 Clock Waveforms RCO TAI WaveformsICO 154 Programmable Interface Waveforms TDI, TMS Ieee 1149.1 Interface WaveformsAm79C930 155 156 AC Test Reference WaveformsPcmcia AC Test Reference Waveform V Non-PCMCIA AC Test Reference Waveform NON-PCMCIA AC Test Reference Waveform 158 Physical DimensionsPQT144 Pin Thin Quad Flat Pack measured in millimeters Typical Am79C930 System Application Device Configuration Frame Reception Frame Transmission Trademarks