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Am79C930
CLOCK WAVEFORMS
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AMD
P R E L I M I N A R Y
152
Am79C930
CLOCK WAVEFORMS
20138B-17
CLKIN
0.8 V
2.0 V
t
CLIN
t
INHL
t
CLKIN
t
INLH
t
CHIN
0.8 V
TXC
0.8 V
2.0 V
t
CLTX
t
TXHL
t
TXC
t
TXLH
t
CHTX
0.8 V
RXC
0.8 V
2.0 V
t
CLRX
t
RXHL
t
RXC
t
RXLH
t
CHRX
0.8 V
Figure 11. CLOCK Timing Diagram
Contents
Main
Am79C930
GENERAL DESCRIPTION
DISTINCTIVE CHARACTERISTICS
PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
ORDERING INFORMATION Standard Products
Am79C930 3
PCMCIA Mode
Bus Interface Unit
Transceiver Attachment Interface Unit
TABLE OF CONTENTS
Page
Page
Page
Page
Page
Page
PCMCIA CONNECTION DIAGRAM
20183B-4
Notes:
PCMCIA PIN SUMMARY Listed by Pin Number
PCMCIA PIN LIST Listed by Pin Name
PCMCIA PIN FUNCTION SUMMARY PCMCIA Pin Summary
Page
PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued)
Output Driver Types
Input Types
ISA PLUG AND PLAY BLOCK DIAGRAM
ISA PLUG AND PLAY CONNECTION DIAGRAM
20183B-6
Notes:
ISA PLUG AND PLAY PIN LIST Listed by Pin Number
ISA PLUG AND PLAY PIN LIST Listed by Pin Name
ISA PLUG AND PLAY PIN SUMMARY
ISA PLUG AND PLAY PIN SUMMARY (continued)
Output Driver Types
Input Types
PIN DESCRIPTIONS Pins with Internal Pull Up or Pull Down Devices
Configuration Pins PCMCIA
Host System Interface Pins
A140
CE1
D70
OE
REG
RESET
STSCHG
WAIT
WE
IOR
IOW
floated
driven
MEMR
CLKIN
PMX[12]
RXCIN
RXC
TXC
HFCLK
HFPE
LFCLK
LFPE
LLOCKE
TXMOD
TXPE
USER7
ACT
ADREF
TCK
TDI
Note: A/D must be disabled.
TDO
TMS
VSS
VDDU1
VSSU1
VDDU2
VDDP
Pin 1: USER2/LA19
Pin 2: USER3/SA16
Pin 3: USER4/LA17
Pin 45: STSCHG/BALE
Pin 90: USER0/RFRSH
Pin 91: USER1/IRQ12/EXTCTS/EXINT188
Pin 92: USER7/IRQ11
Pin 94: RXC/IRQ10/EXTA2DST
Pin 95: USER6/IRQ5/EXTSDF
Pin 96: USER5/IRQ4/EXTCHBSY
Pin 98: ACT
Pin 100: LNK
Pin 101: SDCLK
Pin 102: SDDATA
Pin 103: SDSEL3
Pin 105: SDSEL2
Pin 107: SDSEL1
Pin 115: TXC
Pin 118: LFPE
Pin 120: HFPE
Pin 122: RXPE
Pin 126: TXCMD
Pin 129: TXPE
Pin 131: TXMOD
Pin 132: ANTSLT
Pin 141: ANTSLT/LA23
Pin 142: TXCMD/LA21
Pin 143: TXDATA/LA20
Pin 144: LLOCKE/SA15
FUNCTIONAL DESCRIPTION Basic Functions
Detailed Functions
Bus Interface Unit
PCMCIA Interface
only
ISA (IEEE P996) Plug and Play Interface
sometimes
ISA Plug and Play section.
Memory Interface
Embedded 80188
Media Access Management
Medium Allocation
Initialization
SRAM Memory Management
only
Note that these steps MUST be performed in the order given
Flash Memory Management
MAC Firmware Resources
Transceiver Attachment Interface Unit Management
Bus Interface Unit Interaction
TX FIFO
TX Power Ramp Control
Am79C930-based TX Power Ramp Control
Page
Transceiver-Based TX Power Ramp Control
TX CRC Generation
TX Status
Start of Frame Delimiter Detection
RX Data Parallelization
RX Status Reporting
Bit Ordering
Physical Header Accommodation
DC Bias Control
Baud Determination Logic
multi- plied by the
count
multiplied by the
Clear Channel Assessment Logic
Automatic Antenna Diversity Logic
Baud Determination
TXC As Input
transceiver output
Boundary Scan Circuit
TAP FSM
Supported Instructions
All unused instruc- tion decodes are reserved.
Instruction Register and Decoding Logic
up
Applicability to IEEE 802.11 Power Down Modes
Am79C930 System Interface Resources
PCMCIA Mode Resources
no
PCMCIA Common Memory Resources
some- times
Page
Page
Page
ISA Plug and Play Mode Resources
no
sometimes
Page
Page
Am79C930 Device ISA Plug And Play Mode I/O MAP
*IOBA = ISA Plug and Play I/O Base Address **X = Dont Care
Page
Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set
MAC Firmware Resources
MAC (80188 core) Memory Resources
Page
MAC (80188 core) Memory Resources Restrictions
MAC (80188 core) Interrupt Channel Allocation
MAC (80188 core) DMA Channel Allocation
except
Page
REGISTER DESCRIPTIONS
System Interface Registers (SIR space)
Page
Page
Page
MAC Interface Registers (MIR Space)
Page
Do not write to this register or unexpected consequences will result.
Page
Page
Page
Transceiver Attachment Interface Registers (TIR Space)
mode. TIR uses eight I/O addresses:
88 Am79C930
*XX = Dont care.
mode. TIR uses 32 I/O addresses:
Multi-Function Pin
Page
Page
Page
Page
Page
spaces
TX Power Ramp Control
Multi-Func- tion Pin
Page
Page
Page
Page
Note: Antenna diversity is disabled with the ANTSEN bit (bit 3 of TIR26).
intended for use
Page
Do not write to this register.
TAI Configuration Register Space (TCR)
Page
Page
Page
Page
Page
Page
Page
Page
Page
THIS FUNCTION IS ONLY AVAILABLE IN PCMCIA MODE.
Page
nominal
Page
end
before
Page
Page
Page
Page
Multi- Function Pin
PCMCIA CCR Registers and PCMCIA CIS Space
Page
DC CHARACTERISTICS 5.0 V Am79C930 DC Characteristics
DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics
3.3 V Am79C930 DC CHARACTERISTICS
DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics
IEEE 1149.1 DC CHARACTERISTICS (5.0 and 3.3 V)
5.0 AND 3.3 V PCMCIA INTERFACE
PCMCIA MEMORY READ ACCESS
PCMCIA MEMORY WRITE ACCESS
PCMCIA I/O READ ACCESS
PCMCIA I/O WRITE ACCESS
5.0 AND 3.3 V ISA INTERFACE
ISA ACCESS
5.0 V MEMORY BUS INTERFACE
MEMORY BUS READ ACCESS
MEMORY BUS WRITE ACCESS
Notes: 1.
,
= one of:
3.3 V MEMORY BUS INTERFACE
MEMORY BUS READ ACCESS
MEMORY BUS WRITE ACCESS
Notes: 1.
,
= one of:
5.0 V TAI INTERFACE
5.0 V TAI INTERFACE AC CHARACTERISTICS
Page
3.3 V TAI INTERFACE
3.3 V TAI INTERFACE AC CHARACTERISTICS
5.0 AND 3.3 V USER PROGRAMMABLE PINS
5.0 AND 3.3 V IEEE 1149.1 INTERFACE
ANALOG-TO-DIGITAL (A/D) CONVERTER CHARACTERISTICS
148 Am79C930
TIMING WAVEFORMS PCMCIA Bus Interface Waveforms
Figure 4. PCMCIA MEMORY READ Access Timing Diagram
Figure 5. PCMCIA MEMORY WRITE Access Timing Diagram
Figure 6. PCMCIA I/O READ Access Timing Diagram
Figure 7. PCMCIA I/O WRITE Access Timing Diagram
150 Am79C930
ISA Bus Interface Waveforms
Figure 8. ISA All Access Timing Diagram
,
= one of:
**
Memory Bus Interface Waveforms
Figure 9. Memory Bus READ Access Timing Diagram
Figure 10. Memory Bus WRITE Access Timing Diagram
152 Am79C930
CLOCK WAVEFORMS
Figure 11. CLOCK Timing Diagram
TAI WAVEFORMS
**ICO = Internally Controlled Output
Figure 13. Serial Data Timing Diagram
Figure 12. TAI Timing Diagram
154 Am79C930
PROGRAMMABLE INTERFACE WAVEFORMS
Figure 14. Programmable Interface Timing Diagram
**RCO = Register Controlled Output
IEEE 1149.1 INTERFACE WAVEFORMS
AC TEST REFERENCE WAVEFORMS 5.0 V PCMCIA AC Test Reference Waveform
3.3 V PCMCIA AC Test Reference Waveform
5.0 V NON-PCMCIA AC TEST REFERENCE WAVEFORM
3.3 V NON-PCMCIA AC TEST REFERENCE WAVEFORM
PHYSICAL DIMENSIONS PQT144 144-Pin Thin Quad Flat Pack (measured in millimeters)
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Typical Am79C930 System Application
utilities present in the system must be disabled before attempting this procedure.
Device Configuration
Normal system configuration utilities must be dis- abled before this is attempted.
Frame Transmission
Frame Reception