Tir, SIR110 ISA Plug Core, Play, TIR Register Name | AMD Am79C930

P R E L I M I N A R Y	AMD

TIR mapping with SIR1 bit 2 (EIOW) set to “0” = normal TIR window mode. Note that EIOW = 0 is the only setting

of EIOW that is allowed while operating in ISA PnP mode. TIR uses eight I/O addresses:

TIR		SIR1[1:0]		ISA Plug	80188 Core
Register		(TAI Bank	PCMCIA	and Play	Address in
Number	TIR Register Name	Select)	I/O Address	I/O Address	Memory

0	Network Control	00	0008h	IOBA+0008h	mem 400h
1	Network Status	00	0009h	IOBA+0009h	mem 401h
2	Serial Device	00	000Ah	IOBA+000Ah	mem 402h
3	Fast Serial Port Control	00	000Bh	IOBA+000Bh	mem 403h
4	Interrupt Register 1	00	000Ch	IOBA+000Ch	mem 404h

5	Interrupt Register 2	00	000Dh	IOBA+000Dh	mem 405h

6	Interrupt Mask 1	00	000Eh	IOBA+000Eh	mem 406h
7	Interrupt Mask 2	00	000Fh	IOBA+000Fh	mem 407h

8	Transmit Control	01	0008h	IOBA+0008h	mem 408h
9	Transmit Status	01	0009h	IOBA+0009h	mem 409h

10	TX FIFO Data	01	000Ah	IOBA+000Ah	mem 40Ah

11	Transmit Sequence Control	01	000Bh	IOBA+000Bh	mem 40Bh

12	Byte Counter LSB	01	000Ch	IOBA+000Ch	mem 40Ch

13	Byte Counter MSB	01	000Dh	IOBA+000Dh	mem 40Dh
14	Byte Counter Limit LSB	01	000Eh	IOBA+000Eh	mem 40Eh
15	Byte Counter Limit MSB	01	000Fh	IOBA+000Fh	mem 40Fh

16	Receiver Control	10	0008h	IOBA+0008h	mem 410h
17	Receiver Status	10	0009h	IOBA+0009h	mem 411h
18	RX FIFO Data	10	000Ah	IOBA+000Ah	mem 412h
19	Antenna Slot	10	000Bh	IOBA+000Bh	mem 413h
20	CRC32 Correct Count LSB	10	000Ch	IOBA+000Ch	mem 414h

21	CRC32 Correct Count MSB	10	000Dh	IOBA+000Dh	mem 415h

22	CRC8 Correct Count LSB	10	000Eh	IOBA+000Eh	mem 416h

23	CRC8 Correct Count MSB	10	000Fh	IOBA+000Fh	mem 417h

24	Configuration Index	11	0008h	IOBA+0008h	mem 418h
25	Configuration Data Port	11	0009h	IOBA+0009h	mem 419h

26	Antenna Diversity & A/D	11	000Ah	IOBA+000Ah	mem 41Ah

27	SAR	11	000Bh	IOBA+000Bh	mem 41Bh

28	RSSI Lower Limit	11	000Ch	IOBA+000Ch	mem 41Ch

29	USER Pin Data	11	000Dh	IOBA+000Dh	mem 41Dh
30	Dummy Register	11	000Eh	IOBA+000Eh	mem 41Eh
31	TEST Register	11	000Fh	IOBA+000Fh	mem 41Fh

Am79C930

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Image 87

AMD Am79C930 manual Tir, SIR110 ISA Plug Core, Play, TIR Register Name, Sar

Contents

Am79C930 Speed Optional ProcessingOperating Conditions Package Type Rxdata Reset PcmciaJtag Trst TMS/T3 Adref INT1 IreqSIR0 MIR0 MIR1 SIR1 MIR15 SIR7 Srdy MUX IRQTIR0 TCR0 Fifo TIR31 TCR31 Table of Contents E L I M I N a R Y AMD TX Fifo RX FifoTAP FSM Register Descriptions TIR31 Test 126 Absolute Maximum Ratings AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Txpe TP1 Lfpe PTS1Hfpe PTS1 TP1, PTS1 Name Type LoadName Type Size of Pullup Size of Pulldown DRQ0 Txcmd Ieee Memr Reset LNK ACT CLK20 Test PwrdwnIeee Sddata Bale ISA Plug and Play Connection Diagram SD2 SD4 SD7SD6 SD5 TCK Adref SD5 Vsst ResetSA1 ACT SDSEL2 ADIN1 PTS3/OD2 SD7-SD0 ISA Plug and Play PIN Summary Pcmcia Pins with Internal Pull Up or Pull Down DevicesConfiguration Pins PIN Descriptions Input/Output Host System Interface PinsA14-0 D7-0 Iochrdy ResetAEN Bale MA16-0 IRQ4,5,9-12MD7-0 RXC ClkinPwrdwn Rxcin Rxdata HfclkLfclk Llocke Sddata USER7Adref Sdclk VDD5 TCKAvss TDI VDDU2 VSSVDDU1 VSSU1 Pin 45 STSCHG/BALE Pin 1 USER2/LA19Pin 2 USER3/SA16 Pin 3 USER4/LA17 Pin 92 USER7/IRQ11 Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 94 RXC/IRQ10/EXTA2DST Pin 95 USER6/IRQ5/EXTSDFPin 96 USER5/IRQ4/EXTCHBSY Pin 100 LNK Pin 98 ACT Pin 105 SDSEL2 Pin 101 SdclkPin 102 Sddata Pin 103 SDSEL3 Pin 122 Rxpe Pin 115 TXCPin 118 Lfpe Pin 120 Hfpe Pin 132 Antslt Pin 126 TxcmdPin 129 Txpe Pin 131 Txmod Pin 142 TXCMD/LA21 Pin 143 TXDATA/LA20Pin 144 LLOCKE/SA15 Bus Interface Unit Functional DescriptionBasic Functions Detailed Functions E L I M I N a R Y AMD AMD E L I M I N a R Y Memory Interface EmbeddedMedium Allocation AMD E L I M I N a R Y Flash Memory Management Transceiver Attachment Interface Unit ManagementBus Interface Unit Interaction Transceiver Attachment Interface Unit TX Power Ramp Control Tbclk = Tsclk X Pin Timing Reference Name When RCEN=0 When RCEN=1 RX Data Parallelization TX CRC GenerationTX Status Start of Frame Delimiter Detection RX Status Reporting Bit OrderingRssi A/D Unit Adda Enext Ensar UXA2DST Physical Header AccommodationDC Bias Control Baud Determination Logic Clear Channel Assessment Logic Rssi = Rssi Current CCA result is reported in the Chbsy bit of TIR26Automatic Antenna Diversity Logic Ubdcs Urssi Ieee 1149.1 Test Access Port Interface TXC As InputUbdsd Urssi Stpen Instruction Register and Decoding Logic Power Down FunctionBoundary Scan Circuit Supported Instructions E L I M I N a R Y AMD Applicability to Ieee 802.11 Power Down Modes Software AccessAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Resource Requirements Description of Reserved Use Am79C930 Device Pcmcia Mode Common Memory Restricted SpacePcmcia Address Size Physical Memory SIR153 XXX Am79C930 Device Pcmcia Mode Attribute Memory Map Pcmcia Address Attribute Memory Am79C930 Device Pcmcia Mode I/O MAP ISA Plug and Play Mode ResourcesPcmcia ISA Address in Memory SIR153 Size of Space Physical Memory Am79C930 Device ISA Plug And Play Mode Memory MapKbytes of memory Memory Range Memory Size ISA Address Size Physical Memory AMD E L I M I N a R Y Resource Name Am79C930 Device ISA Plug And Play Mode I/O MAPPhysical ISA SIR1 Readdata Port Name ISA Ieee P996 I/O Address AccessAddress Writedata Address ISA Plug and Play Plug and Play Port Register Name MAC Firmware Resources Physical Location of Memory Active INT0 TAI INT1 BIU Interrupt Channel Allocation in the 80188 CoreAddress Active Size Interrupt Channel Interrupt Source Loopback Operation Reset MethodsReset Pin DMA Channel Allocation In The 80188 Core Coreset SIR06 ISA PnP Reset Register DescriptionsSres TIR05 System Interface Registers SIR space Bit Name Reset Value Description SIR0 General Configuration Register GCR SIR1 Bank Switching Select Register BSS SIR3 Local Memory Address Register 148 LMA Bit Name Reset Value Description IODPA70MD70 during system interface accesses to Flash and Sram SIR2 Local Memory Address Register 70 LMA MAC Interface Registers MIR Space SIR5 I/O Data Port B IodpbMIR0 Processor Interface Register PIR MIR2 Power Down Length Count 70 Pdlc MIR1 Power Up Clock Time 30 Puct MIR5 Free Count 70 Fcnt MIR3 Power Down Length Count 158 PdlcMIR4 Power Down Length Count 2216 Pdlc Permarest MIR9 TCR Mask Stschg Data MIR8 Flash Wait StatesHostallow FLASHWAIT10 Stschgd SRAMWAIT10Hostlongwait Initdn Undefined data MIR10 ReservedThis register is reserved Reserved. Must be written as a 0. Reads of this bit produce Transceiver Attachment Interface Registers TIR Space TIR Register Name TIRSIR110 ISA Plug Core Play SIR110 Core TIR1 Network Status TIR0 Network Control TIR2 Serial Device Antsw TIR3 Fast Serial Port ControlTIR4 Interrupt Register Chbsyc TIR5 Interrupt Register TIR7 Interrupt Unmask Register TIR6 Interrupt Unmask Register TIR8 Transmit Control Txbsy TIR9 Transmit StatusTxcrc Txsdd TIR11 Transmit Sequence Control TIR12 Byte Count Register LSB TIR13 Byte Count Register MSBTIR14 Byte Count Limit LSB TIR15 Byte Count Limit MSB TIR16 Receiver ControlTIR17 Receive Status Register TIR20 CRC32 Correct Byte Count LSB RxbsyTIR18 RX Fifo Data Register TIR19 Reserved TIR21 CRC32 Correct Byte Count MSB TIR22 CRC8 Correct Byte Count LSBTIR23 CRC8 Correct Byte Count MSB TIR24 TCR Index Register TIR25 Configuration Data PortBit Name Reset Value Description CD70 By the current setting of the Configuration Index Register TIR27 Serial Approximation Register AddaSrcs Strtc TIR30 Test Dummy Register Bit Name Reset ValueTIR28 Rssi Lower Limit TIR29 User Pin Data TAI Configuration Register Space TCR TCR0 Network ConfigurationThese bit must be set to 0. Do not write to this register TCR1 Transmit Configuration 01h Bit Name Reset Value DescriptionAm79C930 105 03h TCR2 Clock RecoveryTCR3 Receive Configuration 02h 05h TCR4 Antenna Diversity Timer04h TCR5 TX Ramp Up Timing 07h TCR6 TX Ramp Down Timing06h TCR7 Pin Data a Txdatald U1INTCNTTxcmdt Antsltld 08h Bit Name Reset Value Description SDLT70 00hBit Name Reset Value Description SDLT158 00h TCR8 Start Delimiter LSB 0Ch TCR11 Interrupt Register0Bh TCR12 Interrupt Unmask Register 0Eh TCR13 Pin Configuration aTCR14 Pin Configuration B 0Dh TCR15 Pin Configuration C 0FhAm79C930 113 10h ActenStschgfn TCR16 Baud Detect Start TCR18 Baud Detect Upper Limit 11h Bit Name Reset Value Description12h Bit Name Reset Value Description Undefined data BDLLT50 TCR20 Baud Detect Accept Count for Stop Diversity TCR19 Baud Detect Accept Count for Carrier Sense13h BDCS50 TCR23 Baud Detect Fail Count 15h Bit Name Reset Value Description BDRN30TCR22 Baud Detect Accept Count 16h 19h TCR25 Rssi Configuration18h SS50 00h CACT=TIR277 Analog-to-Digital State Machine Timing Am79C930 119 TCR26 Reserved 1Ah1Bh TCR28 Clear Channel Assessment Configuration 1Ch Bit Name Reset Value DescriptionAm79C930 121 TCR29 Reserved 1Dh1Eh TCR31 Device Revision 1Fh DescriptionAm79C930 123 Pcmcia CCR Registers and Pcmcia CIS Space Pcmcia Configuration Option RegisterSreset Pcmcia Card Configuration and Status Register Am79C930 125 Vice actually enters the power down mode InterruptTil the interrupt has been serviced not pulse generated Pcmcia Card Information Structure CIS Commercial C Devices DC CharacteristicsAm79C930 DC Characteristics Absolute Maximum Ratings Operating Ranges DC Characteristics Am79C930 DC Characteristics Am79C930 127Parameter Description Test Conditions Min Max To 3.6 Temperature TA C to + 70C Supply VoltagesAbsolute Maximum Ratings VDDP, VDD5 Am79C930 129 130 Ieee 1149.1 DC Characteristics 5.0 and 3.3 Pcmcia Memory Read Access Am79C930 131Unit 132 Pcmcia Memory Write Access Am79C930 133 Pcmcia I/O Read Access 134 Pcmcia I/O Write Access Am79C930 135 136 ISA Access Am79C930 137 Memory BUS Read Access 138 Memory BUS Write Access Am79C930 139 140 Am79C930 141 AC Characteristics TAI Interface Absolute Maximum Ratings TAI Interface AC Characteristics Max Unit142 Am79C930 143 144 Am79C930 145 146 Clkin ↓ ANALOG-TO-DIGITAL A/D Converter Characteristics Am79C930 147TCK − Din Timing WaveformsPcmcia Bus Interface Waveforms REG Pcmcia I/O Read Access Timing Diagram 150 ISA Bus Interface Waveforms Clkin Clkout Memory Bus Interface Waveforms 152 Clock Waveforms TAI Waveforms ICORCO 154 Programmable Interface Waveforms Ieee 1149.1 Interface Waveforms Am79C930 155TDI, TMS AC Test Reference Waveforms Pcmcia AC Test Reference Waveform156 V Non-PCMCIA AC Test Reference Waveform NON-PCMCIA AC Test Reference Waveform Physical Dimensions PQT144 Pin Thin Quad Flat Pack measured in millimeters158 Typical Am79C930 System Application Device Configuration Frame Reception Frame Transmission Trademarks