AMD Am79C930 ISA PLUG AND PLAY PIN LIST Listed by Pin Name

22 Am79C930

PRELIMINARY

ISA PLUG AND PLAY PIN LIST Listed by Pin Name

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

ACT 98 MA11 6 SA1 47 SDSEL2 105

ADIN1 134 MA12 15 SA10 71 SDSEL3 103

ADIN2 135 MA13 10 SA11 69 TCK 84

ADREF 137 MA14 12 SA12 56 TDI 88

AEN 48 MA15 14 SA12 56 TDO 85

ANTSLT 132 MA16 13 SA13 64 TEST 81

AVDD 138 MA2 24 SA14 63 TMS 86

AVSS 136 MA3 23 SA15 144 TRST 87

BALE 45 MA4 22 SA16 2 TXC 115

CLK20 80 MA5 20 SA2 49 TXCMD 126

FCE 40 MA6 19 SA3 51 TXDATA 121

FDET 128 MA7 18 SA4 53 TXMOD 131

HFCLK 119 MA8 9 SA5 59 TXPE 129

HFPE 120 MA9 8 SA6 60 V

CC

17

IOCHRDY 52 MD0 27 SA7 54 V

CC

89

IOR 67 MD1 28 SA8 65 VDD5 139

IOW 66 MD2 30 SA9 68 VDDM 4

IRQ10 94 MD3 31 SAR0 108 VDDM 16

IRQ11 92 MD4 33 SAR1 109 VDDM 29

IRQ12 91 MD5 34 SAR2 110 VDDP 55

IRQ4 96 MD6 35 SAR3 111 VDDT 104

IRQ5 95 MD7 36 SAR4 112 VDDT 125

IRQ9 61 MEMR 70 SAR5 113 VDDU1 97

LA17 3 MEMW 62 SAR6 114 VDDU2 140

LA18 72 MOE 38 SCE 39 V

SS

57

LA19 1 MWE 11 SD0 43 V

SS

127

LA20 143 PCMCIA 79 SD1 42 VSSM 7

LA21 142 PMX1 83 SD2 41 VSSM 32

LA22 50 PMX2 82 SD3 78 VSSP 44

LA23 141 PWRDWN 133 SD4 77 VSSP 76

LFCLK 117 RESET 58 SD5 75 VSST 99

LFPE 118 RFRSH 90 SD6 74 VSST 106

LNK 100 RXCIN 124 SD7 73 VSST 116

MA0 26 RXDATA 123 SDCLK 101 VSST 130

MA1 25 RXPE 122 SDDATA 102 VSSU1 93

MA10 37 SA0 46 SDSEL1 107 XCE 5

Contents

Main Am79C930 GENERAL DESCRIPTION DISTINCTIVE CHARACTERISTICS PCnet-Mobile Single-Chip Wireless LAN Media Access Controller ORDERING INFORMATION Standard Products Am79C930 3 PCMCIA Mode Bus Interface Unit Transceiver Attachment Interface Unit TABLE OF CONTENTS Page Page Page Page Page Page PCMCIA CONNECTION DIAGRAM 20183B-4 Notes: PCMCIA PIN SUMMARY Listed by Pin Number PCMCIA PIN LIST Listed by Pin Name PCMCIA PIN FUNCTION SUMMARY PCMCIA Pin Summary Page PCMCIA PIN FUNCTION SUMMARY (continued) PCMCIA Pin Summary (continued) Output Driver Types Input Types ISA PLUG AND PLAY BLOCK DIAGRAM ISA PLUG AND PLAY CONNECTION DIAGRAM 20183B-6 Notes: ISA PLUG AND PLAY PIN LIST Listed by Pin Number ISA PLUG AND PLAY PIN LIST Listed by Pin Name ISA PLUG AND PLAY PIN SUMMARY ISA PLUG AND PLAY PIN SUMMARY (continued) Output Driver Types Input Types PIN DESCRIPTIONS Pins with Internal Pull Up or Pull Down Devices Configuration Pins PCMCIA Host System Interface Pins A140 CE1 D70 OE REG RESET STSCHG WAIT WE IOR IOW floated driven MEMR CLKIN PMX[12] RXCIN RXC TXC HFCLK HFPE LFCLK LFPE LLOCKE TXMOD TXPE USER7 ACT ADREF TCK TDI Note: A/D must be disabled. TDO TMS VSS VDDU1 VSSU1 VDDU2 VDDP Pin 1: USER2/LA19 Pin 2: USER3/SA16 Pin 3: USER4/LA17 Pin 45: STSCHG/BALE Pin 90: USER0/RFRSH Pin 91: USER1/IRQ12/EXTCTS/EXINT188 Pin 92: USER7/IRQ11 Pin 94: RXC/IRQ10/EXTA2DST Pin 95: USER6/IRQ5/EXTSDF Pin 96: USER5/IRQ4/EXTCHBSY Pin 98: ACT Pin 100: LNK Pin 101: SDCLK Pin 102: SDDATA Pin 103: SDSEL3 Pin 105: SDSEL2 Pin 107: SDSEL1 Pin 115: TXC Pin 118: LFPE Pin 120: HFPE Pin 122: RXPE Pin 126: TXCMD Pin 129: TXPE Pin 131: TXMOD Pin 132: ANTSLT Pin 141: ANTSLT/LA23 Pin 142: TXCMD/LA21 Pin 143: TXDATA/LA20 Pin 144: LLOCKE/SA15 FUNCTIONAL DESCRIPTION Basic Functions Detailed Functions Bus Interface Unit PCMCIA Interface only ISA (IEEE P996) Plug and Play Interface sometimes ISA Plug and Play section. Memory Interface Embedded 80188 Media Access Management Medium Allocation Initialization SRAM Memory Management only Note that these steps MUST be performed in the order given Flash Memory Management MAC Firmware Resources Transceiver Attachment Interface Unit Management Bus Interface Unit Interaction TX FIFO TX Power Ramp Control Am79C930-based TX Power Ramp Control Page Transceiver-Based TX Power Ramp Control TX CRC Generation TX Status Start of Frame Delimiter Detection RX Data Parallelization RX Status Reporting Bit Ordering Physical Header Accommodation DC Bias Control Baud Determination Logic multi- plied by the count multiplied by the Clear Channel Assessment Logic Automatic Antenna Diversity Logic Baud Determination TXC As Input transceiver output Boundary Scan Circuit TAP FSM Supported Instructions All unused instruc- tion decodes are reserved. Instruction Register and Decoding Logic up Applicability to IEEE 802.11 Power Down Modes Am79C930 System Interface Resources PCMCIA Mode Resources no PCMCIA Common Memory Resources some- times Page Page Page ISA Plug and Play Mode Resources no sometimes Page Page Am79C930 Device ISA Plug And Play Mode I/O MAP *IOBA = ISA Plug and Play I/O Base Address **X = Dont Care Page Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set MAC Firmware Resources MAC (80188 core) Memory Resources Page MAC (80188 core) Memory Resources Restrictions MAC (80188 core) Interrupt Channel Allocation MAC (80188 core) DMA Channel Allocation except Page REGISTER DESCRIPTIONS System Interface Registers (SIR space) Page Page Page MAC Interface Registers (MIR Space) Page Do not write to this register or unexpected consequences will result. Page Page Page Transceiver Attachment Interface Registers (TIR Space) mode. TIR uses eight I/O addresses: 88 Am79C930 *XX = Dont care. mode. TIR uses 32 I/O addresses: Multi-Function Pin Page Page Page Page Page spaces TX Power Ramp Control Multi-Func- tion Pin Page Page Page Page Note: Antenna diversity is disabled with the ANTSEN bit (bit 3 of TIR26). intended for use Page Do not write to this register. TAI Configuration Register Space (TCR) Page Page Page Page Page Page Page Page Page THIS FUNCTION IS ONLY AVAILABLE IN PCMCIA MODE. Page nominal Page end before Page Page Page Page Multi- Function Pin PCMCIA CCR Registers and PCMCIA CIS Space Page DC CHARACTERISTICS 5.0 V Am79C930 DC Characteristics DC CHARACTERISTICS (continued) 5.0 V Am79C930 DC Characteristics 3.3 V Am79C930 DC CHARACTERISTICS DC CHARACTERISTICS (continued) 3.3 V Am79C930 DC Characteristics IEEE 1149.1 DC CHARACTERISTICS (5.0 and 3.3 V) 5.0 AND 3.3 V PCMCIA INTERFACE PCMCIA MEMORY READ ACCESS PCMCIA MEMORY WRITE ACCESS PCMCIA I/O READ ACCESS PCMCIA I/O WRITE ACCESS 5.0 AND 3.3 V ISA INTERFACE ISA ACCESS 5.0 V MEMORY BUS INTERFACE MEMORY BUS READ ACCESS MEMORY BUS WRITE ACCESS Notes: 1. , = one of: 3.3 V MEMORY BUS INTERFACE MEMORY BUS READ ACCESS MEMORY BUS WRITE ACCESS Notes: 1. , = one of: 5.0 V TAI INTERFACE 5.0 V TAI INTERFACE AC CHARACTERISTICS Page 3.3 V TAI INTERFACE 3.3 V TAI INTERFACE AC CHARACTERISTICS 5.0 AND 3.3 V USER PROGRAMMABLE PINS 5.0 AND 3.3 V IEEE 1149.1 INTERFACE ANALOG-TO-DIGITAL (A/D) CONVERTER CHARACTERISTICS 148 Am79C930 TIMING WAVEFORMS PCMCIA Bus Interface Waveforms Figure 4. PCMCIA MEMORY READ Access Timing Diagram Figure 5. PCMCIA MEMORY WRITE Access Timing Diagram Figure 6. PCMCIA I/O READ Access Timing Diagram Figure 7. PCMCIA I/O WRITE Access Timing Diagram 150 Am79C930 ISA Bus Interface Waveforms Figure 8. ISA All Access Timing Diagram , = one of: ** Memory Bus Interface Waveforms Figure 9. Memory Bus READ Access Timing Diagram Figure 10. Memory Bus WRITE Access Timing Diagram 152 Am79C930 CLOCK WAVEFORMS Figure 11. CLOCK Timing Diagram TAI WAVEFORMS **ICO = Internally Controlled Output Figure 13. Serial Data Timing Diagram Figure 12. TAI Timing Diagram 154 Am79C930 PROGRAMMABLE INTERFACE WAVEFORMS Figure 14. Programmable Interface Timing Diagram **RCO = Register Controlled Output IEEE 1149.1 INTERFACE WAVEFORMS AC TEST REFERENCE WAVEFORMS 5.0 V PCMCIA AC Test Reference Waveform 3.3 V PCMCIA AC Test Reference Waveform 5.0 V NON-PCMCIA AC TEST REFERENCE WAVEFORM 3.3 V NON-PCMCIA AC TEST REFERENCE WAVEFORM PHYSICAL DIMENSIONS PQT144 144-Pin Thin Quad Flat Pack (measured in millimeters) *For reference only. BSC is an ANSI standard for Basic Space Centering. Typical Am79C930 System Application utilities present in the system must be disabled before attempting this procedure. Device Configuration Normal system configuration utilities must be dis- abled before this is attempted. Frame Transmission Frame Reception