MIR1 Power Up Clock Time 30 Puct | AMD Am79C930 instruction

			P R E L I M I N A R Y	AMD

4	PDC	0	Power Down Command. When PDC is set to 1, the power down cy-
			cle of the BIU power down state machine will begin. PDC will auto-
			matically clear itself after completion of the power down operation.
3	SYSINT	0	System Interrupt. SYSINT Indicates a 1 after the system issues an
			interrupt command to the 80188 core by writing to the INT2EC bit of
			the GCR register (SIR0). SYSINT will become cleared to a 0 when
			the 80188 core writes a 1 to SYSINT.
2	INT2SYS	0	Interrupt To System. When INT2SYS is set to a 1, an interrupt is
			generated to the system, provided that the ECWAIT bit (SIR0[4]0 is
			set to 0. INT2SYS will stay set at 1 until the system clears it by
			writing a 1 to ECINT (bit 3 of SIR0). Writing a 0 to INT2SYS will have
			no effect.
1	SYSINTM	0	System Interrupt Mask. When SYSINTM is set to a 1, system-gen-
			erated interrupts (through the SYSINT bit of MIR0) are allowed to
			be passed to the 80188. When SYSINTM is reset to 0, no
			system-generated interrupts will be passed to the 80188.
0	PWDNDN	0	Power Down Done. When Power Down mode is completed, then
			PWDNDN will automatically become set to 1 and an interrupt to the
			80188 core will be generated. The 80188 core may clear the
			PWDNDN bit by first writing a 1 to PWDNDN and then writing a 0 to
			PWDNDN. Note that PWDNDN will read as a 0, after writing a 1 to
			PWDNDN, but a 0 must still be written to PWDNDN in order to com-
			plete the reset operation. If a 0 is not written to PWDNDN, then the
			PWDNDN will be permanently held in reset.

MIR1: Power Up Clock Time [3:0] (PUCT)

This register is used to determine the length of time that will be used to allow the CLKIN buffer circuit to power up and stabilize before the end of the power down cycle.

The length of the power up phase will be the value of the PUCT times 0.5 msec.

Bit	Name	Reset Value	Description

7:4	PUCT[3:0]	0000b	Length of the power up stabilization time for the CLKIN buffer cir-
			cuitry. The resolution of the power up clock timer is in increments of
			16x (Period of PMX). The nominal PMX1/2 crystal value is
			32.768 kHz, resulting in a resolution of 16 x 31.25 μs = 500 μs.
3:0	Reserved	–	Reserved. Must be written as a 0. Reads of this bit produce
			undefined data.

MIR2: Power Down Length Count [7:0] (PDLC)

This register is used to determine the length of power down cycles. Before execution of the power down se- quence, the 80188 core must load the PDLC counter.

Upon execution of the power down sequence, the PDLC value will be counted down to zero and the power down cycle will end.

Bit	Name	Reset Value	Description

0	PDLC[7:0]	00h	Lower 8 bits of the length of the power down cycle counter. The
			resolution of the power down length counter is in increments of
			PMX1/2 periods. The nominal PMX1/2 crystal Value is 32.768 kHz,
			resulting in a resolution of 31.25 μs.

Am79C930

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Image 81

AMD Am79C930 manual MIR1 Power Up Clock Time 30 Puct, MIR2 Power Down Length Count 70 Pdlc

Contents

Am79C930 Operating Conditions Optional ProcessingPackage Type Speed Jtag Trst TMS/T3 Reset PcmciaAdref Rxdata SIR0 MIR0 MIR1 SIR1 MIR15 SIR7 IreqSrdy INT1 TIR0 TCR0 IRQFifo TIR31 TCR31 MUX Table of Contents E L I M I N a R Y AMD TX Fifo RX FifoTAP FSM Register Descriptions TIR31 Test 126 Absolute Maximum Ratings AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Hfpe PTS1 Lfpe PTS1TP1, PTS1 Txpe TP1 Name Type LoadName Type Size of Pullup Size of Pulldown Ieee Sddata Reset LNK ACT CLK20 Test PwrdwnBale DRQ0 Txcmd Ieee Memr ISA Plug and Play Connection Diagram SD6 SD7SD5 SD2 SD4 SA1 SD5 Vsst ResetACT SDSEL2 ADIN1 TCK Adref PTS3/OD2 SD7-SD0 ISA Plug and Play PIN Summary Configuration Pins Pins with Internal Pull Up or Pull Down DevicesPIN Descriptions Pcmcia A14-0 Host System Interface PinsD7-0 Input/Output AEN ResetBale Iochrdy MA16-0 IRQ4,5,9-12MD7-0 Pwrdwn ClkinRxcin RXC Lfclk HfclkLlocke Rxdata Adref USER7Sdclk Sddata Avss TCKTDI VDD5 VDDU1 VSSVSSU1 VDDU2 Pin 2 USER3/SA16 Pin 1 USER2/LA19Pin 3 USER4/LA17 Pin 45 STSCHG/BALE Pin 92 USER7/IRQ11 Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 94 RXC/IRQ10/EXTA2DST Pin 95 USER6/IRQ5/EXTSDFPin 96 USER5/IRQ4/EXTCHBSY Pin 100 LNK Pin 98 ACT Pin 102 Sddata Pin 101 SdclkPin 103 SDSEL3 Pin 105 SDSEL2 Pin 118 Lfpe Pin 115 TXCPin 120 Hfpe Pin 122 Rxpe Pin 129 Txpe Pin 126 TxcmdPin 131 Txmod Pin 132 Antslt Pin 142 TXCMD/LA21 Pin 143 TXDATA/LA20Pin 144 LLOCKE/SA15 Basic Functions Functional DescriptionDetailed Functions Bus Interface Unit E L I M I N a R Y AMD AMD E L I M I N a R Y Memory Interface EmbeddedMedium Allocation AMD E L I M I N a R Y Flash Memory Management Transceiver Attachment Interface Unit ManagementBus Interface Unit Interaction Transceiver Attachment Interface Unit TX Power Ramp Control Tbclk = Tsclk X Pin Timing Reference Name When RCEN=0 When RCEN=1 TX Status TX CRC GenerationStart of Frame Delimiter Detection RX Data Parallelization RX Status Reporting Bit OrderingRssi A/D Unit DC Bias Control Physical Header AccommodationBaud Determination Logic Adda Enext Ensar UXA2DST Clear Channel Assessment Logic Automatic Antenna Diversity Logic Current CCA result is reported in the Chbsy bit of TIR26Ubdcs Urssi Rssi = Rssi Ieee 1149.1 Test Access Port Interface TXC As InputUbdsd Urssi Stpen Boundary Scan Circuit Power Down FunctionSupported Instructions Instruction Register and Decoding Logic E L I M I N a R Y AMD Applicability to Ieee 802.11 Power Down Modes Software AccessAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Resource Requirements Pcmcia Address Size Physical Memory Am79C930 Device Pcmcia Mode Common Memory Restricted SpaceSIR153 Description of Reserved Use XXX Am79C930 Device Pcmcia Mode Attribute Memory Map Pcmcia Address Attribute Memory Am79C930 Device Pcmcia Mode I/O MAP ISA Plug and Play Mode ResourcesPcmcia Kbytes of memory Am79C930 Device ISA Plug And Play Mode Memory MapMemory Range Memory Size ISA Address in Memory SIR153 Size of Space Physical Memory ISA Address Size Physical Memory AMD E L I M I N a R Y Physical Am79C930 Device ISA Plug And Play Mode I/O MAPISA SIR1 Resource Name Address Port Name ISA Ieee P996 I/O Address AccessWritedata Readdata Address ISA Plug and Play Plug and Play Port Register Name MAC Firmware Resources Physical Location of Memory Active Address Active Size Interrupt Channel Allocation in the 80188 CoreInterrupt Channel Interrupt Source INT0 TAI INT1 BIU Reset Pin Reset MethodsDMA Channel Allocation In The 80188 Core Loopback Operation Coreset SIR06 ISA PnP Reset Register DescriptionsSres TIR05 System Interface Registers SIR space Bit Name Reset Value Description SIR0 General Configuration Register GCR SIR1 Bank Switching Select Register BSS MD70 during system interface accesses to Flash and Sram Bit Name Reset Value Description IODPA70SIR2 Local Memory Address Register 70 LMA SIR3 Local Memory Address Register 148 LMA MAC Interface Registers MIR Space SIR5 I/O Data Port B IodpbMIR0 Processor Interface Register PIR MIR2 Power Down Length Count 70 Pdlc MIR1 Power Up Clock Time 30 Puct MIR4 Power Down Length Count 2216 Pdlc MIR3 Power Down Length Count 158 PdlcPermarest MIR5 Free Count 70 Fcnt Hostallow MIR8 Flash Wait StatesFLASHWAIT10 MIR9 TCR Mask Stschg Data Hostlongwait SRAMWAIT10Initdn Stschgd This register is reserved MIR10 ReservedReserved. Must be written as a 0. Reads of this bit produce Undefined data Transceiver Attachment Interface Registers TIR Space SIR110 ISA Plug Core TIRPlay TIR Register Name SIR110 Core TIR1 Network Status TIR0 Network Control TIR2 Serial Device TIR4 Interrupt Register TIR3 Fast Serial Port ControlChbsyc Antsw TIR5 Interrupt Register TIR7 Interrupt Unmask Register TIR6 Interrupt Unmask Register TIR8 Transmit Control Txcrc TIR9 Transmit StatusTxsdd Txbsy TIR11 Transmit Sequence Control TIR12 Byte Count Register LSB TIR13 Byte Count Register MSBTIR14 Byte Count Limit LSB TIR15 Byte Count Limit MSB TIR16 Receiver ControlTIR17 Receive Status Register TIR18 RX Fifo Data Register RxbsyTIR19 Reserved TIR20 CRC32 Correct Byte Count LSB TIR21 CRC32 Correct Byte Count MSB TIR22 CRC8 Correct Byte Count LSBTIR23 CRC8 Correct Byte Count MSB Bit Name Reset Value Description CD70 TIR25 Configuration Data PortBy the current setting of the Configuration Index Register TIR24 TCR Index Register Srcs AddaStrtc TIR27 Serial Approximation Register TIR28 Rssi Lower Limit Bit Name Reset ValueTIR29 User Pin Data TIR30 Test Dummy Register TAI Configuration Register Space TCR TCR0 Network ConfigurationThese bit must be set to 0. Do not write to this register TCR1 Transmit Configuration 01h Bit Name Reset Value DescriptionAm79C930 105 TCR3 Receive Configuration TCR2 Clock Recovery02h 03h 04h TCR4 Antenna Diversity TimerTCR5 TX Ramp Up Timing 05h 06h TCR6 TX Ramp Down TimingTCR7 Pin Data a 07h Txcmdt U1INTCNTAntsltld Txdatald Bit Name Reset Value Description SDLT158 00h Bit Name Reset Value Description SDLT70 00hTCR8 Start Delimiter LSB 08h 0Bh TCR11 Interrupt RegisterTCR12 Interrupt Unmask Register 0Ch TCR14 Pin Configuration B TCR13 Pin Configuration a0Dh 0Eh TCR15 Pin Configuration C 0FhAm79C930 113 Stschgfn ActenTCR16 Baud Detect Start 10h 12h Bit Name Reset Value Description 11h Bit Name Reset Value DescriptionUndefined data BDLLT50 TCR18 Baud Detect Upper Limit 13h TCR19 Baud Detect Accept Count for Carrier SenseBDCS50 TCR20 Baud Detect Accept Count for Stop Diversity TCR22 Baud Detect Accept Count 15h Bit Name Reset Value Description BDRN3016h TCR23 Baud Detect Fail Count 18h TCR25 Rssi ConfigurationSS50 00h 19h CACT=TIR277 Analog-to-Digital State Machine Timing Am79C930 119 TCR26 Reserved 1Ah1Bh TCR28 Clear Channel Assessment Configuration 1Ch Bit Name Reset Value DescriptionAm79C930 121 TCR29 Reserved 1Dh1Eh TCR31 Device Revision 1Fh DescriptionAm79C930 123 Sreset Pcmcia Configuration Option RegisterPcmcia Card Configuration and Status Register Pcmcia CCR Registers and Pcmcia CIS Space Til the interrupt has been serviced not pulse generated Vice actually enters the power down mode InterruptPcmcia Card Information Structure CIS Am79C930 125 Am79C930 DC Characteristics DC CharacteristicsAbsolute Maximum Ratings Operating Ranges Commercial C Devices DC Characteristics Am79C930 DC Characteristics Am79C930 127Parameter Description Test Conditions Min Max Absolute Maximum Ratings Temperature TA C to + 70C Supply VoltagesVDDP, VDD5 To 3.6 Am79C930 129 130 Ieee 1149.1 DC Characteristics 5.0 and 3.3 Pcmcia Memory Read Access Am79C930 131Unit 132 Pcmcia Memory Write Access Am79C930 133 Pcmcia I/O Read Access 134 Pcmcia I/O Write Access Am79C930 135 136 ISA Access Am79C930 137 Memory BUS Read Access 138 Memory BUS Write Access Am79C930 139 140 Am79C930 141 AC Characteristics TAI Interface Absolute Maximum Ratings TAI Interface AC Characteristics Max Unit142 Am79C930 143 144 Am79C930 145 146 Clkin ↓ ANALOG-TO-DIGITAL A/D Converter Characteristics Am79C930 147TCK − Pcmcia Bus Interface Waveforms Timing WaveformsREG Din Pcmcia I/O Read Access Timing Diagram 150 ISA Bus Interface Waveforms Clkin Clkout Memory Bus Interface Waveforms 152 Clock Waveforms TAI Waveforms ICORCO 154 Programmable Interface Waveforms Ieee 1149.1 Interface Waveforms Am79C930 155TDI, TMS AC Test Reference Waveforms Pcmcia AC Test Reference Waveform156 V Non-PCMCIA AC Test Reference Waveform NON-PCMCIA AC Test Reference Waveform Physical Dimensions PQT144 Pin Thin Quad Flat Pack measured in millimeters158 Typical Am79C930 System Application Device Configuration Frame Reception Frame Transmission Trademarks