AMD P R E L I M I N A R Y
56 Am79C930
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the
Am79C930 device:
Boundary Scan CircuitThe boundary scan test circuit uses five pins: TRST,
TCK, TMS, TDI, and TDO. These five pins are collec-
tively labeled the TAP. The boundary scan test circuit in-
cludes a finite state machine (FSM), an instruction
register, and a data register array. Internal pull-up resis-
tors are provided for the TDI and TMS pins. The TCK pin
must not be left unconnected.
TAP FSMThe TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power up or after H_RESET.
The TRST pin is supported in order to ensure that the
FSM is in the TEST_LOGIC_RESET state before test-
ing is begun.
Supported InstructionsIn addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), one
additional instruction (IDCODE) is provided as addi-
tional support for board level testing.
All unused instruc-tion decodes are reserved.Instruction Name Instruction Code Mode Selected Data Register Description
EXTEST 0000 Test BSR External Test
ID_CODE 0001 Normal ID REG ID Code Inspection
SAMPLE 0010 Normal BSR Sample Boundary
Reserved 0011–1110 Reserved Reserved Reserved
BYPASS 1111 Normal Bypass Bypass Scan
Instruction Register and Decoding LogicAfter H_RESET or S_RESET, the IDCODE instruction
is always loaded into the IEEE 1149.1 register. The de-
coding logic gives signals to control the data flow in the
DATA registers according to the current instruction.
Boundary Scan Register (BSR)Each BSR cell has two stages. A flip-flop and a latch
are used for the SERIAL SHIFT STAGE and for the
PARALLEL OUTPUT STAGE, respectively.
There are four possible operation modes in the
BSR cell:
1 Capture
2 Shift
3 Update
4 System Function
Other Data Registers(1) BYPASS REGISTER (1 BIT)
(2) DEVICE ID REGISTER (32 BITS)
(3) INSCAN0
Device ID Register Contents:
Bits 31–28: Version
Bits 27–12: Part Number (0010 1000 0101 0000)
Bits 11–1: Manufacturer ID. The 11 bit manufacturer
ID code for AMD is 00000000001 in accor-
dance with JEDEC publication 106-A.
Bit 0: Always a logic 1
This is an internal scan path for AMD internal
testing use.
Power Saving Modes
Power Down FunctionThe Am79C930 BIU includes five registers that are used
to invoke a power-down function that will support the
IEEE 802.11 (draft) specified power down by allowing
variable lengths of power-down and power-up time. The
registers include the Processor Interface Register
(MIR0), which contains the Power Down command bit, a
Power Down Length Count set of registers (MIR2,3,4),
and a Power Up Clock Timer (MIR1) register. The power
down sequence is executed by the firmware running
on the embedded 80188, either independently, or in
response to a request from the host. In the PCMCIA