P R E L I M I N A R Y | AMD |
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be high assert, such that when the TGAP2 counter expires, the TXMOD pin will be driven to a HIGH logic level.
TCR28: Clear Channel Assessment Configuration
This register is the Clear Channel Assessment Configuration register. The bits in this register are used
to determine which features will be used to determine clear channel assessment.
CONFIGURATION REGISTER INDEX: | 1Ch |
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Bit | Name | Reset Value | Description |
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7 | RXCFN | 0 | RXC Function. When RXCFN is set to a 1, then the RXC pin will be | ||
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| driven with the internal RXC clock value, regardless of its source. | ||
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| That is, the RXC source may be either the result of the DPLL locking | ||
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| operation, or it may directly reflect the value of the RXCIN pin, de- | ||
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| pending upon the selection of the ECLK bit of TCR2. |
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| Complete control of the function of the RXC/IRQ10 pin is described | ||
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| in the |
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6 | ENXSDF | 0 | Enable External Start Delimiter Found. When ENXSDF is set to a 1, | ||
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| then the internal SDF result is not used. Instead, the value of the | ||
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| USER6/IRQ5 pin is used as the source for SDF indication. When | ||
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| ENXSDF is set to 1, then changes to the value of the USER6/IRQ5 | ||
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| pin are used to determine the status of the SDF interrupt of TIR5 (bit | ||
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| 2). When ENXSDF is set to 0, then the source for SDF indication is | ||
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| the internal SDF determination logic. The current drive and function | ||
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| settings for the USER6/IRQ5 pin have no effect on the use of the | ||
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| value of this pin for the SDF function. |
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5 | ENXCHBSY | 0 | Enable External CHBSY. When ENXCHBSY is set to a 1, then the | ||
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| internal CCA result is not used. Instead, the value of the | ||
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| USER5/IRQ4 pin is used as the source for CCA information. When | ||
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| ENXCHBSY is set to 1, the value of the USER5/IRQ4 pin is used to | ||
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| set the value of the CHBSY bit of TIR26 (bit 7), and changes to | ||
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| the value of the USER5/IRQ4 pin are used to determine the status | ||
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| of the CHBSYC interrupt of TIR4 (bit 7) and the BCF interrupt bit | ||
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| of TIR5. |
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| When ENXCHBSY is set to a 1, then antenna diversity switching is | ||
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| disabled and the receive function of the Am79C930 device must be | ||
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| enabled by a positive indication of SDF on the USER6/IRQ5 | ||
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| input pin. |
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| When ENXCHBSY is set to 0, then the source for CCA indication is | ||
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| the internal CCA determination logic. The current drive and function | ||
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| settings for the USER6/IRQ5 pin have no effect on the use of the | ||
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| value of this pin for the SDF function. |
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4 | RUPD | 0 | Receive Use Preamble Detect. When RUPD is set to a 1, then the | ||
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| stop diversity decision is used to enable the receive state machine. | ||
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| That is, when the decision is made to stop switching antenna selec- | ||
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| tions, then the receive state machine will enable the receive data | ||
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| path to the RX FIFO. When RUPD is reset to a 0, then the receive | ||
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| data path to the RX FIFO is enabled when SFD is detected. |
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3 | STPEN | 0 | Stop Antenna Diversity Enable. Setting this bit to a 1 allows | ||
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| the clear channel assessment logic to stop the antenna | ||
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| diversity operation. |
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2 | UBDSD | 0 | Use Baud Detect of Stop Diversity in Antenna Diversity decision. | ||
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| When this bit is set to a 1, the Baud Detect Count for Stop Diversity | ||
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| becomes one input to the stop diversity decision logic. When this bit | ||
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| Am79C930 | 121 | |
