
AMD | P R E L I M I N A R Y |
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The SRAM is intended to serve as a shared memory re- source between the driver operating through the system interface and the 80188 core operating through the Am79C930 memory interface bus. Even though SRAM memory locations 0 0400h through 0 043Fh are acces- sible from the system interface, these locations cannot be used for
ISA Plug and Play I/O Resources — The Am79C930 device occupies 16 bytes of I/O space. The
The Local Memory Address port plus SIR1[5:3] function together as a pointer to the memory resources of the Am79C930 device. SIR1[5] determines the device se- lected (SRAM or Flash) and SIR1[4:3], and LMA[14:0] supply the address to the selected device whenever the I/O Data Port is read or written. Whenever any of the I/O Data Ports is accessed, then the Local Memory Address Port value is automatically incremented by a value of 1.
The next table indicates the mapping of all I/O resources that are accessible through the Am79C930 ISA system interface.
Note that some resources are physically located within the BIU, while others are located in the TAI, and still oth- ers exist as external Flash and SRAM. Also note that additional registers for ISA Plug and Play exist in the BIU and are indirectly accessed through the Plug and Play ADDRESS, WRITE_DATA, and READ_DATA ports. All resources are 1 byte in width.
When accessing Am79C930 I/O resources through ISA I/O cycle accesses, the upper 8 bits of the ISA system address will be ignored. Only the lower 16 bits of address will be used to check for a match of the address range assigned to the Am79C930 device by the Plug and Play configuration program (i.e., the I/O Base Ad- dress = IOBA). (The Plug and Play configuration pro- gram will have written an I/O base address value into the I/O Base Address registers (Plug and Play ports 60h and 61h) following system boot up and
66 | Am79C930 |