TIR21 CRC32 Correct Byte Count MSB | AMD Am79C930 manual

AMDP R E L I M I N A R Y

TIR21: CRC32 Correct Byte Count MSB

This register is the CRC32 Correct Byte Count

MSB register.

Bit	Name	Reset Value		Description

7–4	Reserved	–		Reserved. Must be written as a 0. Reads of this bit produce
				undefined data.
3–0	C32C[11:8]	–		CRC32 Correct Count. The value in this register indicates the upper
				4 bits of the 12-bit byte position when the CRC32 value was last cor-
				rect. CRC32 value 001h corresponds to the first byte of the received
				message following the Start of Frame Delimiter. If the value in this
				register (and TIR20) does not match the length value indicated in
				the frame header (plus overhead for PHY and MAC headers and
				CRC) for frames that employ 32-bit CRC values, then the frame
				should be rejected by the MAC firmware. Note that all bytes begin-
				ning with the first byte following the Start of Frame Delimiter and in-
				cluding the CRC bytes are included in the CRC32 Correct Count
				value, but the bytes that are included in the CRC32 calculation are
				dependent upon the setting of the PFL bits of TCR3.
TIR22: CRC8 Correct Byte Count LSB
This register is the CRC8		Correct	Byte	Count
LSB register.
Bit	Name	Reset Value		Description

7–0	C32C[7:0]	–		CRC8 Correct Count. The value in this register indicates the lower 8
				bits of the 12-bit byte position when the CRC8 value was last cor-
				rect. CRC8 value 001h corresponds to the first byte of the received
				message following the Start of Frame Delimiter. If the value in this
				register (and TIR22) does not match the length value indicated in
				the frame header (plus overhead for PHY and MAC headers and
				CRC) for frames that employ 8-bit CRC values, then the frame
				should be rejected by the MAC firmware. Note that all bytes begin-
				ning with the first byte following the Start of Frame Delimiter and in-
				cluding the CRC bytes are included in the CRC8 Correct Count
				value, but the bytes that are included in the CRC8 calculation are
				dependent upon the setting of the PFL bits of TCR3.
TIR23: CRC8 Correct Byte Count MSB
This register is the CRC8		Correct	Byte	Count
MSB register .
Bit	Name	Reset Value		Description

7–4	Reserved	–		Reserved. Must be written as a 0. Reads of this bit produce
				undefined data.
3–0	C8C[11:8]	–		CRC8 Correct Count. The value in this register indicates the upper
				4 of the 12-bit byte position when the CRC8 value was last correct.
				CRC8 value 001h corresponds to the first byte of the received mes-
				sage following the Start of Frame Delimiter. If the value in this regis-
				ter (and TIR22) does not match the length value indicated in the
				frame header (plus overhead for PHY and MAC headers and CRC)
				for frames that employ 8-bit CRC values, then the frame should be
				rejected by the MAC firmware. Note that all bytes beginning with the
				first byte following the Start of Frame Delimiter and including the
				CRC bytes are included in the CRC8 Correct Count value, but the
				bytes that are included in the CRC8 calculation are dependent upon
				the setting of the PFL bits of TCR3.

100				Am79C930

Image 100

AMD Am79C930 TIR21 CRC32 Correct Byte Count MSB, TIR22 CRC8 Correct Byte Count LSB, TIR23 CRC8 Correct Byte Count MSB

Contents

Am79C930 Optional Processing Operating ConditionsPackage Type Speed Reset Pcmcia Jtag Trst TMS/T3Adref Rxdata Ireq SIR0 MIR0 MIR1 SIR1 MIR15 SIR7Srdy INT1 IRQ TIR0 TCR0Fifo TIR31 TCR31 MUX Table of Contents E L I M I N a R Y AMD RX Fifo TX FifoTAP FSM Register Descriptions TIR31 Test Absolute Maximum Ratings 126 AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Lfpe PTS1 Hfpe PTS1TP1, PTS1 Txpe TP1 Load Name TypeName Type Size of Pullup Size of Pulldown Reset LNK ACT CLK20 Test Pwrdwn Ieee SddataBale DRQ0 Txcmd Ieee Memr ISA Plug and Play Connection Diagram SD7 SD6SD5 SD2 SD4 SD5 Vsst Reset SA1ACT SDSEL2 ADIN1 TCK Adref SD7-SD0 PTS3/OD2 ISA Plug and Play PIN Summary Pins with Internal Pull Up or Pull Down Devices Configuration PinsPIN Descriptions Pcmcia Host System Interface Pins A14-0D7-0 Input/Output Reset AENBale Iochrdy IRQ4,5,9-12 MA16-0MD7-0 Clkin PwrdwnRxcin RXC Hfclk LfclkLlocke Rxdata USER7 AdrefSdclk Sddata TCK AvssTDI VDD5 VSS VDDU1VSSU1 VDDU2 Pin 1 USER2/LA19 Pin 2 USER3/SA16Pin 3 USER4/LA17 Pin 45 STSCHG/BALE Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 92 USER7/IRQ11 Pin 95 USER6/IRQ5/EXTSDF Pin 94 RXC/IRQ10/EXTA2DSTPin 96 USER5/IRQ4/EXTCHBSY Pin 98 ACT Pin 100 LNK Pin 101 Sdclk Pin 102 SddataPin 103 SDSEL3 Pin 105 SDSEL2 Pin 115 TXC Pin 118 LfpePin 120 Hfpe Pin 122 Rxpe Pin 126 Txcmd Pin 129 TxpePin 131 Txmod Pin 132 Antslt Pin 143 TXDATA/LA20 Pin 142 TXCMD/LA21Pin 144 LLOCKE/SA15 Functional Description Basic FunctionsDetailed Functions Bus Interface Unit E L I M I N a R Y AMD AMD E L I M I N a R Y Embedded Memory InterfaceMedium Allocation AMD E L I M I N a R Y Transceiver Attachment Interface Unit Management Flash Memory ManagementBus Interface Unit Interaction TX Power Ramp Control Transceiver Attachment Interface Unit Pin Timing Reference Name When RCEN=0 When RCEN=1 Tbclk = Tsclk X TX CRC Generation TX StatusStart of Frame Delimiter Detection RX Data Parallelization Bit Ordering RX Status ReportingRssi A/D Unit Physical Header Accommodation DC Bias ControlBaud Determination Logic Adda Enext Ensar UXA2DST Clear Channel Assessment Logic Current CCA result is reported in the Chbsy bit of TIR26 Automatic Antenna Diversity LogicUbdcs Urssi Rssi = Rssi TXC As Input Ieee 1149.1 Test Access Port InterfaceUbdsd Urssi Stpen Power Down Function Boundary Scan CircuitSupported Instructions Instruction Register and Decoding Logic E L I M I N a R Y AMD Software Access Applicability to Ieee 802.11 Power Down ModesAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Resource Requirements Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Common Memory Restricted Space Pcmcia Address Size Physical MemorySIR153 Description of Reserved Use Am79C930 Device Pcmcia Mode Attribute Memory Map XXX Pcmcia Address Attribute Memory ISA Plug and Play Mode Resources Am79C930 Device Pcmcia Mode I/O MAPPcmcia Am79C930 Device ISA Plug And Play Mode Memory Map Kbytes of memoryMemory Range Memory Size ISA Address in Memory SIR153 Size of Space Physical Memory ISA Address Size Physical Memory AMD E L I M I N a R Y Am79C930 Device ISA Plug And Play Mode I/O MAP PhysicalISA SIR1 Resource Name Port Name ISA Ieee P996 I/O Address Access AddressWritedata Readdata ISA Plug and Play Plug and Play Port Register Name Address MAC Firmware Resources Active Physical Location of Memory Interrupt Channel Allocation in the 80188 Core Address Active SizeInterrupt Channel Interrupt Source INT0 TAI INT1 BIU Reset Methods Reset PinDMA Channel Allocation In The 80188 Core Loopback Operation Coreset SIR06 Register Descriptions ISA PnP ResetSres TIR05 System Interface Registers SIR space SIR0 General Configuration Register GCR Bit Name Reset Value Description SIR1 Bank Switching Select Register BSS Bit Name Reset Value Description IODPA70 MD70 during system interface accesses to Flash and SramSIR2 Local Memory Address Register 70 LMA SIR3 Local Memory Address Register 148 LMA SIR5 I/O Data Port B Iodpb MAC Interface Registers MIR SpaceMIR0 Processor Interface Register PIR MIR1 Power Up Clock Time 30 Puct MIR2 Power Down Length Count 70 Pdlc MIR3 Power Down Length Count 158 Pdlc MIR4 Power Down Length Count 2216 PdlcPermarest MIR5 Free Count 70 Fcnt MIR8 Flash Wait States HostallowFLASHWAIT10 MIR9 TCR Mask Stschg Data SRAMWAIT10 HostlongwaitInitdn Stschgd MIR10 Reserved This register is reservedReserved. Must be written as a 0. Reads of this bit produce Undefined data Transceiver Attachment Interface Registers TIR Space TIR SIR110 ISA Plug CorePlay TIR Register Name SIR110 Core TIR0 Network Control TIR1 Network Status TIR2 Serial Device TIR3 Fast Serial Port Control TIR4 Interrupt RegisterChbsyc Antsw TIR5 Interrupt Register TIR6 Interrupt Unmask Register TIR7 Interrupt Unmask Register TIR8 Transmit Control TIR9 Transmit Status TxcrcTxsdd Txbsy TIR11 Transmit Sequence Control TIR13 Byte Count Register MSB TIR12 Byte Count Register LSBTIR14 Byte Count Limit LSB TIR16 Receiver Control TIR15 Byte Count Limit MSBTIR17 Receive Status Register Rxbsy TIR18 RX Fifo Data RegisterTIR19 Reserved TIR20 CRC32 Correct Byte Count LSB TIR22 CRC8 Correct Byte Count LSB TIR21 CRC32 Correct Byte Count MSBTIR23 CRC8 Correct Byte Count MSB TIR25 Configuration Data Port Bit Name Reset Value Description CD70By the current setting of the Configuration Index Register TIR24 TCR Index Register Adda SrcsStrtc TIR27 Serial Approximation Register Bit Name Reset Value TIR28 Rssi Lower LimitTIR29 User Pin Data TIR30 Test Dummy Register TCR0 Network Configuration TAI Configuration Register Space TCRThese bit must be set to 0. Do not write to this register 01h Bit Name Reset Value Description TCR1 Transmit ConfigurationAm79C930 105 TCR2 Clock Recovery TCR3 Receive Configuration02h 03h TCR4 Antenna Diversity Timer 04hTCR5 TX Ramp Up Timing 05h TCR6 TX Ramp Down Timing 06hTCR7 Pin Data a 07h U1INTCNT TxcmdtAntsltld Txdatald Bit Name Reset Value Description SDLT70 00h Bit Name Reset Value Description SDLT158 00hTCR8 Start Delimiter LSB 08h TCR11 Interrupt Register 0BhTCR12 Interrupt Unmask Register 0Ch TCR13 Pin Configuration a TCR14 Pin Configuration B0Dh 0Eh 0Fh TCR15 Pin Configuration CAm79C930 113 Acten StschgfnTCR16 Baud Detect Start 10h 11h Bit Name Reset Value Description 12h Bit Name Reset Value DescriptionUndefined data BDLLT50 TCR18 Baud Detect Upper Limit TCR19 Baud Detect Accept Count for Carrier Sense 13hBDCS50 TCR20 Baud Detect Accept Count for Stop Diversity 15h Bit Name Reset Value Description BDRN30 TCR22 Baud Detect Accept Count16h TCR23 Baud Detect Fail Count TCR25 Rssi Configuration 18hSS50 00h 19h Analog-to-Digital State Machine Timing Am79C930 119 CACT=TIR277 1Ah TCR26 Reserved1Bh 1Ch Bit Name Reset Value Description TCR28 Clear Channel Assessment ConfigurationAm79C930 121 1Dh TCR29 Reserved1Eh 1Fh Description TCR31 Device RevisionAm79C930 123 Pcmcia Configuration Option Register SresetPcmcia Card Configuration and Status Register Pcmcia CCR Registers and Pcmcia CIS Space Vice actually enters the power down mode Interrupt Til the interrupt has been serviced not pulse generatedPcmcia Card Information Structure CIS Am79C930 125 DC Characteristics Am79C930 DC CharacteristicsAbsolute Maximum Ratings Operating Ranges Commercial C Devices Am79C930 127 DC Characteristics Am79C930 DC CharacteristicsParameter Description Test Conditions Min Max Temperature TA C to + 70C Supply Voltages Absolute Maximum RatingsVDDP, VDD5 To 3.6 Am79C930 129 Ieee 1149.1 DC Characteristics 5.0 and 3.3 130 Am79C930 131 Pcmcia Memory Read AccessUnit Pcmcia Memory Write Access 132 Pcmcia I/O Read Access Am79C930 133 Pcmcia I/O Write Access 134 Am79C930 135 ISA Access 136 Memory BUS Read Access Am79C930 137 Memory BUS Write Access 138 Am79C930 139 140 AC Characteristics TAI Interface Absolute Maximum Ratings Am79C930 141 Max Unit TAI Interface AC Characteristics142 Am79C930 143 144 Am79C930 145 Clkin ↓ 146 Am79C930 147 ANALOG-TO-DIGITAL A/D Converter CharacteristicsTCK − Timing Waveforms Pcmcia Bus Interface WaveformsREG Din Pcmcia I/O Read Access Timing Diagram ISA Bus Interface Waveforms 150 Memory Bus Interface Waveforms Clkin Clkout Clock Waveforms 152 ICO TAI WaveformsRCO Programmable Interface Waveforms 154 Am79C930 155 Ieee 1149.1 Interface WaveformsTDI, TMS Pcmcia AC Test Reference Waveform AC Test Reference Waveforms156 NON-PCMCIA AC Test Reference Waveform V Non-PCMCIA AC Test Reference Waveform PQT144 Pin Thin Quad Flat Pack measured in millimeters Physical Dimensions158 Device Configuration Typical Am79C930 System Application Frame Transmission Frame Reception Trademarks