P R E L I M I N A R Y | AMD |
|
|
ENXCHBSY bit of TCR28 and the CHBSYU bit of TIR5 and operates independently of the bits in the table below.
In addition to the functionality listed above, the USER5/IRQ4/EXTCHBSY pin may be used as the source for CCA information, instead of relying on the in- ternal CCA logic of the Am79C930 device. When using the external CCA information, CCA information from the internal logic will be unavailable. External CCA informa- tion will appear in the same register bit locations as in- ternal CCA information, when enabled, so a change from internal source to external source will be transpar- ent to firmware (excepting the necessary change in the ENXCHBSY bit value).
This source of CCA information is controlled by the ENXCHBSY bit of TCR28. When the ENXCHBSY bit of TCR28 is set to a 1, then the value of the USER5/IRQ4/EXTCHBSY pin will be fed directly to the CHBSYC bit of TIR4, CHBSY bit of TIR26 and the BCF bit of TIR5. If the CHBSYC interrupt is unmasked, it will produce an interrupt to the 80188 embedded controller. If the BCF interrupt is unmasked, it will produce an inter- rupt to the 80188 embedded controller. Note that setting the ENXCHBSY bit of TCR28 to a 1 will cause the USER5/IRQ4/EXTCHBYS pin to function as an input, regardless of the settings of the other control bits listed.
|
|
|
|
|
| USER5/ | USER5/ |
PCMCIA | ENXCHBSY | USER5FN | USER5EN | IRQ Select | IRQ Type | IRQ4 | IRQ4 |
Pin | TCR28[5] | TCR7[5] | TCR15[2] | PnPx70 | PnPx71 | Direction | Pin Data |
|
|
|
|
|
|
|
|
0 | 1 | X | X | X | X | I | TIR11[5] |
|
|
|
|
|
|
|
|
0 | 0 | 0 | X | 4h | 2h | O | IRQ4 |
|
|
|
|
|
|
|
|
0 | 0 | 0 | X | 4h | 1h | OD | IRQ4 |
|
|
|
|
|
|
|
|
0 | 0 | 0 | 0 | ≠4h | X | I | TIR11[5] |
|
|
|
|
|
|
|
|
0 | 0 | 0 | 1 | ≠4h | X | O | TIR11[5] |
|
|
|
|
|
|
|
|
0 | 0 | 1 | 0 | X | X | I | TIR11[5] |
|
|
|
|
|
|
|
|
0 | 0 | 1 | 1 | X | X | O | TIR11[5] |
|
|
|
|
|
|
|
|
1 | 1 | X | X | X | X | I | TIR11[5] |
|
|
|
|
|
|
|
|
1 | 0 | X | 0 | X | X | I | TIR11[5] |
|
|
|
|
|
|
|
|
1 | 0 | X | 1 | X | X | O | TIR11[5] |
Pin 98: ACT
The ACT pin may be configured for input or output op- eration. The output drive may be programmed for totem pole or open drain operation. ACT pin configuration is accomplished according to the following table:
Note that a read of the ACT bit (TIR0[6]) will always give the current ACT pin value, regardless of pin configuration setting.
ACTEN | ACT | ACTDR | ACT Pin | ACT Pin |
|
TCR15[1] | TIR0[6] | TCR27[3] | Direction | Value |
|
|
|
|
|
|
|
0 | X | X | I | NA |
|
1 | 0 | 0 | OD | float | reset default condition |
|
|
|
|
|
|
1 | 1 | 0 | OD | LOW |
|
|
|
|
|
|
|
1 | 0 | 1 | O | HIGH |
|
|
|
|
|
|
|
1 | 1 | 1 | O | LOW |
|
|
|
|
|
|
|
Pin 100: LNK
The LNK pin may be configured for input or output op- eration. The output drive may be programmed for totem pole or open drain operation. LNK pin configuration is accomplished according to the following table:
Note that a read of the LNK bit (TIR0[7]) will always give the current LNK pin value, regardless of pin configuration setting.
LNKEN | LNK | LNKDR | LNK Pin | LNK Pin |
| |
TCR13[7] | TIR0[7] | TCR27[4] | Direction |
| Value |
|
|
|
|
|
|
|
|
0 | X | X | I |
| NA |
|
1 | 0 | 0 | OD |
| float | reset default condition |
|
|
|
|
|
|
|
1 | 1 | 0 | OD |
| LOW |
|
1 | 0 | 1 | O |
| HIGH |
|
|
|
|
|
|
|
|
1 | 1 | 1 | O |
| LOW |
|
|
|
|
|
|
|
|
|
|
| Am79C930 |
| 37 | |
