TCR6 TX Ramp Down Timing, 06h, TCR7 Pin Data a, 07h | AMD Am79C930

AMD	P R E L I M I N A R Y

TCR6: TX Ramp Down Timing

This register is the TX Ramp Down Timing register. This register determines the ramp down timing of the TX enable signals.

CONFIGURATION REGISTER INDEX:			06h
Bit	Name	Reset Value	Description

7:4	TGAP3[3:0]	0h	Transmit Timing Gap 3. These bits are used to determine the gap
			between the deassertion of the T3 signal and the deassertion of the
			T2 signal. T3 and T2 can be used to control the timing of the
			TXMOD and TXPE pins. The interval is programmable with a reso-
			lution equal to 20 times the CLKIN period when the CLKGT20 bit of
			MIR9 is set to 0 and a resolution equal to 40 times the CLKIN period
			when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with
			CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 μ.
3:0	TGAP4[3:0]	0h	Transmit Timing Gap 4. These bits are used to determine the gap
			between the deassertion of the T2 signal and the deassertion of the
			T1 signal. T2 and T1 can be used to control the timing of the TXPE
			and TXCMD pins. The interval is programmable with a resolution
			equal to 20 times the CLKIN period when the CLKGT20 bit of MIR9

is set to 0 and a resolution equal to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 μ.

TCR7: Pin Data A

This register is the Pin Data A register. This register is used to deliver and retrieve data from the ANTSLT,

TXDATA and TXCMD pins and to configure the function of the USER5 and USER6 pins.

CONFIGURATION REGISTER INDEX:			07h
Bit	Name	Reset Value	Description

7	CTSEN	0	CTS Enable. When CTSEN is set to a 1, then the USER1/IRQ12 pin
			input value will be used to gate the start of the internal TX state ma-
			chine. With CTSEN set to a 1, T1, T2, etc., signaling will not follow
			the assertion of the TXS bit of TIR8 until USER1/IRQ12/EXTCTS
			becomes active (HIGH), and then normal timing for T1, T2, etc., will
			be produced.
			When CTSEN is set to a 0, then TX state machine operations pro-
			ceed without delay, following the assertion the TXS bit of TIR8, re-
			gardless of the value of USER1/IRQ12/EXTCTS.
6	USER6FN	0	USER6 Function. USER6FN, the PCMCIA mode pin, USER6EN
			(TCR15[3]), and the ISA Plug and Play registers 70h and 71h are
			used to determine the function of the USER6/IRQ5 pin.
			In addition, the USER6/IRQ5 pin may be used to produce interrupts
			to the 80188 embedded controller. This capability is controlled by
			the ENXSDF bit of TCR28 and the SDFU bit of TIR5 and operates
			independently of the bits mentioned above.
			The control of the function of the USER6/IRQ5 pin is described in
			the Multi-Function Pin section.
5	USER5FN	0	USER5 Function. USER5FN, the PCMCIA mode pin, USER5EN
			(TCR15[2]), and ISA PnP registers 70h and 71h are used to deter-
			mine the function of the USER5/IRQ4 pin.

108			Am79C930

Image 108

AMD Am79C930 manual TCR6 TX Ramp Down Timing, 06h, TCR7 Pin Data a, 07h, Ctsen

Contents

Am79C930 Optional Processing Operating ConditionsPackage Type Speed Reset Pcmcia Jtag Trst TMS/T3Adref Rxdata Ireq SIR0 MIR0 MIR1 SIR1 MIR15 SIR7Srdy INT1 IRQ TIR0 TCR0Fifo TIR31 TCR31 MUX Table of Contents E L I M I N a R Y AMD TX Fifo RX FifoTAP FSM Register Descriptions TIR31 Test Absolute Maximum Ratings 126 AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Lfpe PTS1 Hfpe PTS1TP1, PTS1 Txpe TP1 Name Type LoadName Type Size of Pullup Size of Pulldown Reset LNK ACT CLK20 Test Pwrdwn Ieee SddataBale DRQ0 Txcmd Ieee Memr ISA Plug and Play Connection Diagram SD7 SD6SD5 SD2 SD4 SD5 Vsst Reset SA1ACT SDSEL2 ADIN1 TCK Adref SD7-SD0 PTS3/OD2 ISA Plug and Play PIN Summary Pins with Internal Pull Up or Pull Down Devices Configuration PinsPIN Descriptions Pcmcia Host System Interface Pins A14-0D7-0 Input/Output Reset AENBale Iochrdy MA16-0 IRQ4,5,9-12MD7-0 Clkin PwrdwnRxcin RXC Hfclk LfclkLlocke Rxdata USER7 AdrefSdclk Sddata TCK AvssTDI VDD5 VSS VDDU1VSSU1 VDDU2 Pin 1 USER2/LA19 Pin 2 USER3/SA16Pin 3 USER4/LA17 Pin 45 STSCHG/BALE Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 92 USER7/IRQ11 Pin 94 RXC/IRQ10/EXTA2DST Pin 95 USER6/IRQ5/EXTSDFPin 96 USER5/IRQ4/EXTCHBSY Pin 98 ACT Pin 100 LNK Pin 101 Sdclk Pin 102 SddataPin 103 SDSEL3 Pin 105 SDSEL2 Pin 115 TXC Pin 118 LfpePin 120 Hfpe Pin 122 Rxpe Pin 126 Txcmd Pin 129 TxpePin 131 Txmod Pin 132 Antslt Pin 142 TXCMD/LA21 Pin 143 TXDATA/LA20Pin 144 LLOCKE/SA15 Functional Description Basic FunctionsDetailed Functions Bus Interface Unit E L I M I N a R Y AMD AMD E L I M I N a R Y Memory Interface EmbeddedMedium Allocation AMD E L I M I N a R Y Flash Memory Management Transceiver Attachment Interface Unit ManagementBus Interface Unit Interaction TX Power Ramp Control Transceiver Attachment Interface Unit Pin Timing Reference Name When RCEN=0 When RCEN=1 Tbclk = Tsclk X TX CRC Generation TX StatusStart of Frame Delimiter Detection RX Data Parallelization RX Status Reporting Bit OrderingRssi A/D Unit Physical Header Accommodation DC Bias ControlBaud Determination Logic Adda Enext Ensar UXA2DST Clear Channel Assessment Logic Current CCA result is reported in the Chbsy bit of TIR26 Automatic Antenna Diversity LogicUbdcs Urssi Rssi = Rssi Ieee 1149.1 Test Access Port Interface TXC As InputUbdsd Urssi Stpen Power Down Function Boundary Scan CircuitSupported Instructions Instruction Register and Decoding Logic E L I M I N a R Y AMD Applicability to Ieee 802.11 Power Down Modes Software AccessAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Resource Requirements Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Common Memory Restricted Space Pcmcia Address Size Physical MemorySIR153 Description of Reserved Use Am79C930 Device Pcmcia Mode Attribute Memory Map XXX Pcmcia Address Attribute Memory Am79C930 Device Pcmcia Mode I/O MAP ISA Plug and Play Mode ResourcesPcmcia Am79C930 Device ISA Plug And Play Mode Memory Map Kbytes of memoryMemory Range Memory Size ISA Address in Memory SIR153 Size of Space Physical Memory ISA Address Size Physical Memory AMD E L I M I N a R Y Am79C930 Device ISA Plug And Play Mode I/O MAP PhysicalISA SIR1 Resource Name Port Name ISA Ieee P996 I/O Address Access AddressWritedata Readdata ISA Plug and Play Plug and Play Port Register Name Address MAC Firmware Resources Active Physical Location of Memory Interrupt Channel Allocation in the 80188 Core Address Active SizeInterrupt Channel Interrupt Source INT0 TAI INT1 BIU Reset Methods Reset PinDMA Channel Allocation In The 80188 Core Loopback Operation Coreset SIR06 ISA PnP Reset Register DescriptionsSres TIR05 System Interface Registers SIR space SIR0 General Configuration Register GCR Bit Name Reset Value Description SIR1 Bank Switching Select Register BSS Bit Name Reset Value Description IODPA70 MD70 during system interface accesses to Flash and SramSIR2 Local Memory Address Register 70 LMA SIR3 Local Memory Address Register 148 LMA MAC Interface Registers MIR Space SIR5 I/O Data Port B IodpbMIR0 Processor Interface Register PIR MIR1 Power Up Clock Time 30 Puct MIR2 Power Down Length Count 70 Pdlc MIR3 Power Down Length Count 158 Pdlc MIR4 Power Down Length Count 2216 PdlcPermarest MIR5 Free Count 70 Fcnt MIR8 Flash Wait States HostallowFLASHWAIT10 MIR9 TCR Mask Stschg Data SRAMWAIT10 HostlongwaitInitdn Stschgd MIR10 Reserved This register is reservedReserved. Must be written as a 0. Reads of this bit produce Undefined data Transceiver Attachment Interface Registers TIR Space TIR SIR110 ISA Plug CorePlay TIR Register Name SIR110 Core TIR0 Network Control TIR1 Network Status TIR2 Serial Device TIR3 Fast Serial Port Control TIR4 Interrupt RegisterChbsyc Antsw TIR5 Interrupt Register TIR6 Interrupt Unmask Register TIR7 Interrupt Unmask Register TIR8 Transmit Control TIR9 Transmit Status TxcrcTxsdd Txbsy TIR11 Transmit Sequence Control TIR12 Byte Count Register LSB TIR13 Byte Count Register MSBTIR14 Byte Count Limit LSB TIR15 Byte Count Limit MSB TIR16 Receiver ControlTIR17 Receive Status Register Rxbsy TIR18 RX Fifo Data RegisterTIR19 Reserved TIR20 CRC32 Correct Byte Count LSB TIR21 CRC32 Correct Byte Count MSB TIR22 CRC8 Correct Byte Count LSBTIR23 CRC8 Correct Byte Count MSB TIR25 Configuration Data Port Bit Name Reset Value Description CD70By the current setting of the Configuration Index Register TIR24 TCR Index Register Adda SrcsStrtc TIR27 Serial Approximation Register Bit Name Reset Value TIR28 Rssi Lower LimitTIR29 User Pin Data TIR30 Test Dummy Register TAI Configuration Register Space TCR TCR0 Network ConfigurationThese bit must be set to 0. Do not write to this register TCR1 Transmit Configuration 01h Bit Name Reset Value DescriptionAm79C930 105 TCR2 Clock Recovery TCR3 Receive Configuration02h 03h TCR4 Antenna Diversity Timer 04hTCR5 TX Ramp Up Timing 05h TCR6 TX Ramp Down Timing 06hTCR7 Pin Data a 07h U1INTCNT TxcmdtAntsltld Txdatald Bit Name Reset Value Description SDLT70 00h Bit Name Reset Value Description SDLT158 00hTCR8 Start Delimiter LSB 08h TCR11 Interrupt Register 0BhTCR12 Interrupt Unmask Register 0Ch TCR13 Pin Configuration a TCR14 Pin Configuration B0Dh 0Eh TCR15 Pin Configuration C 0FhAm79C930 113 Acten StschgfnTCR16 Baud Detect Start 10h 11h Bit Name Reset Value Description 12h Bit Name Reset Value DescriptionUndefined data BDLLT50 TCR18 Baud Detect Upper Limit TCR19 Baud Detect Accept Count for Carrier Sense 13hBDCS50 TCR20 Baud Detect Accept Count for Stop Diversity 15h Bit Name Reset Value Description BDRN30 TCR22 Baud Detect Accept Count16h TCR23 Baud Detect Fail Count TCR25 Rssi Configuration 18hSS50 00h 19h Analog-to-Digital State Machine Timing Am79C930 119 CACT=TIR277 TCR26 Reserved 1Ah1Bh TCR28 Clear Channel Assessment Configuration 1Ch Bit Name Reset Value DescriptionAm79C930 121 TCR29 Reserved 1Dh1Eh TCR31 Device Revision 1Fh DescriptionAm79C930 123 Pcmcia Configuration Option Register SresetPcmcia Card Configuration and Status Register Pcmcia CCR Registers and Pcmcia CIS Space Vice actually enters the power down mode Interrupt Til the interrupt has been serviced not pulse generatedPcmcia Card Information Structure CIS Am79C930 125 DC Characteristics Am79C930 DC CharacteristicsAbsolute Maximum Ratings Operating Ranges Commercial C Devices DC Characteristics Am79C930 DC Characteristics Am79C930 127Parameter Description Test Conditions Min Max Temperature TA C to + 70C Supply Voltages Absolute Maximum RatingsVDDP, VDD5 To 3.6 Am79C930 129 Ieee 1149.1 DC Characteristics 5.0 and 3.3 130 Pcmcia Memory Read Access Am79C930 131Unit Pcmcia Memory Write Access 132 Pcmcia I/O Read Access Am79C930 133 Pcmcia I/O Write Access 134 Am79C930 135 ISA Access 136 Memory BUS Read Access Am79C930 137 Memory BUS Write Access 138 Am79C930 139 140 AC Characteristics TAI Interface Absolute Maximum Ratings Am79C930 141 TAI Interface AC Characteristics Max Unit142 Am79C930 143 144 Am79C930 145 Clkin ↓ 146 ANALOG-TO-DIGITAL A/D Converter Characteristics Am79C930 147TCK − Timing Waveforms Pcmcia Bus Interface WaveformsREG Din Pcmcia I/O Read Access Timing Diagram ISA Bus Interface Waveforms 150 Memory Bus Interface Waveforms Clkin Clkout Clock Waveforms 152 TAI Waveforms ICORCO Programmable Interface Waveforms 154 Ieee 1149.1 Interface Waveforms Am79C930 155TDI, TMS AC Test Reference Waveforms Pcmcia AC Test Reference Waveform156 NON-PCMCIA AC Test Reference Waveform V Non-PCMCIA AC Test Reference Waveform Physical Dimensions PQT144 Pin Thin Quad Flat Pack measured in millimeters158 Device Configuration Typical Am79C930 System Application Frame Transmission Frame Reception Trademarks