P R E L I M I N A R Y | AMD |
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The sleep state machine is returned to its idle state (i.e., awake).
The following registers and state machines are UNAFFECTED by assertion of the PCMCIA COR SRESET bit of COR[7]:
All TIR registers are unaffected by COR SRESET.
All TCR registers are unaffected by COR SRESET.
All | TAI state | machines | are | unaffected | by |
COR SRESET. |
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The | 80188 | controller | is | unaffected | by |
COR SRESET. |
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It is generally recommended that the SRESET bit of COR[7] should not be SET to a 1 unless the CORESET bit of SIR0[6] has first been set to a 1. This recommen- dation is to insure that the memory bus arbitration state machine is not reset while the 80188 embedded control- ler is executing an access. The proper sequence for us- ing the COR SRESET bit should be:
1.SET the CORESET bit SIR0[6] to a 1.
2.SET the COR SRESET bit PCMCIA COR[7] to a 1.
3.RESET the COR SRESET bit PCMCIA COR[7] to a 0.
4.RESET the CORESET bit SIR0[6] to a 0.
An option to this procedure is to first insure that the 80188 controller is in the HALT state before the COR SRESET bit is asserted. Note however, that the FLASHWAIT and SRAMWAIT values are reset by COR SRESET; therefore, if 80188 operations are re- sumed after the COR SRESET has been performed, the performance of the 80188 may be affected.
The user may decide not to follow these recommenda- tions, but in such a case, it should be recognized that the 80188 may suffer from unpredictable behavior as a result.
ISA PnP RESET
The ISA PnP Configuration Control Register may be used to reset the Am79C930 device. Writing the value “111b” to bits two through zero of this register (i.e., bits [2:0]) will cause an internal RESET pulse to occur within the Am79C930 device). The RESET pulse will last for 14 CLKIN periods.
This RESET will have the same effect as asserting the RESET pin of the Am79C930 device, except that, as stated above, the ISA PnP RESET is limited to a dura- tion of 14 CLKIN periods.
SRES (TIR0[5])
The SRES bit of TIR0[5] can be used to reset the TAI section of the Am79C930 device. When the SRES bit is asserted, then the TAI section of the Am79C930 will be reset.
The following registers and state machines are RESET to their default values by assertion of the SRES bit of TIR0[5]:
(Note that some register locations' default values are UNDEFINED)
All | TIR | registers, except | TIR0[7:0] | which |
is unaffected. |
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All | TCR | registers are reset | to default | values |
by SRES. |
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All TAI state machines are reset to idle states by SRES.
The following registers and state machines are UNAFFECTED by assertion of the SRES bit of TIR[5]:
The sleep state machine is unaffected by SRES.
The memory bus arbitration state machine is unaf- fected by SRES.
All SIR registers are unaffected by SRES.
All MIR registers are unaffected by SRES.
The 80188 controller is unaffected by SRES.
PCMCIA registers are unaffected by SRES.
ISA PnP registers are unaffected by SRES.
The ISA PnP state machine is unaffected by SRES.
REGISTER DESCRIPTIONS
The Am79C930 device has five distinct areas of register storage: System Interface Register (SIR), MAC Inter- face Register (MIR), Transceiver Attachment Interface Unit Register (TIR), Transceiver Attachment Interface Uniit Configuration Register (TCR), and the PCMCIA (or ISA Plug and Play) register sets.
The SIR space contains eight registers which are used by the host driver to control Am79C930 device opera- tions and to collect status, namely, the General Configu- ration Register and the Bank Switching Select Register. The Local Memory Address and Local Memory Data registers may be used instead of
Am79C930 | 75 |
