
P R E L I M I N A R YAMD
PCMCIA I/O READ ACCESS
Parameter |
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Symbol | Parameter Description | Test Conditions | Min | Max | Unit |
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tAVIGL | Address setup to IORD ↓ |
| 70 |
| ns |
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tIGHAX | Address hold from IORD − |
| 20 |
| ns |
tRGLIGL | REG setup to IORD ↓ |
| 5 |
| ns |
tIGHRGH | REG hold from IORD − |
| 0 |
| ns |
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tELIGL | CE setup to IORD ↓ |
| 5 |
| ns |
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tIGHEH | CE hold from IORD − |
| 20 |
| ns |
tIGLIGH | IORD width |
| 165 |
| ns |
tIGLIAL | INPACK ↓ delay from IORD ↓ |
| 0 | 45 | ns |
tIGHIAH | INPACK − delay from IORD − |
|
| 45 | ns |
tIGLWTL | WAIT ↓ delay from IORD ↓ |
|
| 35 | ns |
tWTLWTH | WAIT width | Notes 1, 2 |
| 53 X TCLKIN | ns |
tWTHQV | Data delay from WAIT − |
|
| 0 | ns |
tIGLQNZ | Data enabled from IORD ↓ | Note 2 | 0 |
| ns |
tIGLQV | Data delay from IORD ↓ |
|
| 100 | ns |
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tIGHQX | Data hold from IORD − |
| 0 |
| ns |
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tIGHQZ | Data disabled from IORD − | Note 2 |
| 20 | ns |
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Notes:
1. The max value for this parameter assumes the following worst case situation:
Value | Worst Case |
0FLASH and SRAM wait states set at “3.”
1Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins instruction fetch cycle to FLASH memory.
2PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188 controller access.
3Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM; PCMCIA READ stycle is being held in wait state.
5After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto memory bus to SRAM; host is still held in wait state.
7At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2.Parameter is not included in production test.
Am79C930 | 133 |