AMD Am79C930 PCMCIA PIN FUNCTION SUMMARY PCMCIA Pin Summary

16 Am79C930
PRELIMINARY
PCMCIA PIN FUNCTION SUMMARY
PCMCIA Pin Summary
No. of
Pins Pin Name Pin Function Pin Style
15 A14–A0 PCMCIA address bus lines I
8 D7–D0 PCMCIA data bus lines TS2
1 RESET PCMCIA bus RESET line I
1 CE1 Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write
accesses I
1 OE Output Enable—used to enable the output drivers of the Am79C930 device for
PCMCIA Read accesses I
1 WE Write Enable—used to indicate that the current PCMCIA cycle is a write access I
1 REG REG—used to indicate that the current PCMCIA cycle is to the Attribute
Memory space of the Am79C930 device I
1 INPACK Input Acknowledge—used to indicate that the Am79C930 device will respond
to the current I/O read cycle TS1
1 WAIT Wait—used to delay the termination of the current PCMCIA cycle TS2
1 IORD I/O Read—this signal is asserted by the PCMCIA host system whenever an
I/O read operation occurs
1 IOWR I/O Write—this signal is asserted by the PCMCIA host system whenever an
I/O write operation occurs I
1 IREQ Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software PTS3
1 STSCHG Status Change—PCMCIA output used only for WAKEUP signaling PTS1
1 PCMCIA PCMCIA mode—selects PCMCIA or ISA Plug and Play mode I
1 PWRDWN Powerdown—indicates that device is in the power down mode TP1
17 MA16–0 Memory Address Bus—these lines are used to address locations in the Flash device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design TP1
8 MD7–0 Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design TS1
1 FCE Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface TP1
1 SCE SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface TP1
1 XCE eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface) TP1
1 MOE Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus TP1
1 MWE Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus TP1
1 TCK Test Clock—this is the clock signal for IEEE 1149.1 testing I
1 TDI Test Data In—this is the data input signal for IEEE 1149.1 testing I