AMD Am79C930 manual No. Pins Pin Name Pin Function Pin Style

P R E L I M I N A R Y

PCMCIA PIN FUNCTION SUMMARY

PCMCIA Pin Summary

No. of
Pins		Pin Name	Pin Function	Pin Style
15	A14–A0		PCMCIA address bus lines	I
8	D7–D0		PCMCIA data bus lines	TS2
1	RESET		PCMCIA bus RESET line	I
			Card Enable 1—used to ena ble the D7–0 pins for PCMCIA Read and Write
1	CE1			I
			accesses
			Output Enable—used to ena ble the output drivers of the Am79C930 device for
1	OE			I
			PCMCIA Read accesses
1			Write Enable—used to indicate that the current PCMCIA cycle is a w rite access	I
	WE
			REG—used to indicate that the current PCMCIA cycle is to the Att ribute
1	REG			I
			Memory space of the Am79C930 device
			Input Acknowledge—used to indicate that the Am79C930 d evice will respond
1	INPACK			TS1
			to the current I/O read cycle
1			Wait—used to del ay the termination of the current PCMCIA cycle	TS2
	WAIT
			I/O Read—this signal is asse rted by the PCMCIA host system whenever an
1	IORD
			I/O read operation occurs
			I/O Write—this signal is asse rted by the PCMCIA host system whenever an
1	IOWR			I
			I/O write operation occurs
			Interrupt Request—this line is asse rted when the Am79C930 device needs
1	IREQ			PTS3
			servicing from the software
1			Status Change—PCMCIA output used only for WAKEUP signaling	PTS1
	STSCHG
1	PCMCIA		PCMCIA mode—selects PCMCIA or ISA Plug and Pl ay mode	I
1	PWRDWN		Powerdown—indicates that d evice is in the power down mode	TP1
			Memory Address Bus—these lines are used to address locations in the Flash
17	MA16–0		device, the SRAM device, and an extra peripheral device that are contained	TP1
			within an Am79C930-based design
8	MD7–0		Memory Data Bus—these lines are used to w rite and read data to/from Flash,	TS1
			SRAM, and/or an extra peripheral device within an Am79C930-based design
			Flash Chip Enable—this signal becomes asse rted when the Flash device has
1			been addressed by either the 80188 core of the Am79C930 device or by the	TP1
	FCE
			software through the PCMCIA interface
			SRAM Chip Enable—this signal becomes asse rted when the SRAM device
1			has been addressed by either the 80188 core of the Am79C930 device or by	TP1
	SCE
			the software through the PCMCIA interface
			eXtra Chip Enable—this signal becomes asse rted when the extra peripheral
1			device has been addressed by the 80188 core of the Am79C930 device (XCE	TP1
	XCE
			is not accessible through the system interface)
			Memory Output Enable—this signal becomes asse rted during reads of devices
1	MOE			TP1
			located on the memory interface bus
			Memory Write Enable—this signal becomes asse rted during writes to devices
1	MWE			TP1
			located on the memory interface bus
1	TCK		Test Clock—this is the clo ck signal for IEEE 1149.1 testing	I
1	TDI		Test Data In—this is the data input signal for IEEE 1149.1 testing	I

16 Am79C930