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| P R E L I M I N A R Y |
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6 | Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | |||||
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| undefined data. |
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5:4 | SRAMWAIT[1:0] | 11b |
| These bits must be set equal to or greater than the number of wait | ||||
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| states that are generated internally in the 80188 core as defined by | ||||
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| the programming of the R1 and R0 bits of the 80188 LMCS register. | ||||
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| Wait states programmed into SRAMWAIT will cause wait states to | ||||
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| be inserted into 80188 access to SRAM and system accesses to | ||||
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| SRAM. Each wait state added to an SRAM access is equivalent to | ||||
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| two CLKIN periods. These bits are interpreted as follows. | ||||
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| Number Of Wait |
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| States Used By |
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| Arbitration Logic For |
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| SRAMWAIT[1:0] |
| SRAM |
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| 11 |
| 3 |
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| 10 |
| 2 |
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| 01 |
| 1 |
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| 00 |
| 0 |
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3 | HOSTLONGWAIT | 0 |
| When HOSTLONGWAIT is set to a 1, 96, or 192 CLKIN periods | ||||
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| (depending upon the setting of the CLKGT20 bit of MIR9) of | ||||
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| READY DELAY are added to all system access cycles that are di- | ||||
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| rected to Flash, SRAM and TAI registers. (Note that accesses to | ||||
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| PCMCIA registers, SIR registers and ISA PnP register are unaf- | ||||
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| fected.) This delay is nominally 4.8 μs when CLKIN = 20 MHz and | ||||
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| CLKGT20 is set to 0, and nominally 4.8 μs when CLKIN = 40 MHz | ||||
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| and CLKGT20 is set to 1. |
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| When HOSTLONGWAIT is set to a 0, all host (system) access cy- | ||||
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| cles will be delayed according to their position in the arbitration | ||||
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| queue, where the only other master competing is the 80188 core | ||||
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| and the requesting device has priority over the current master (i.e., | ||||
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| worst case READY delay with HOSTLONGWAIT set to 0 is equal to | ||||
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| 1 access performed by other master plus the number of wait states | ||||
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| for the device being accessed.) | ||||
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| System write accesses will be posted and, therefore, may not im- | ||||
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| mediately experience the “longwait” delay. However, the posted ac- | ||||
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| cess must internally wait for the “longwait“ before becoming | ||||
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| completed and this will cause a subsequent system access to expe- | ||||
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| rience the full 4.8 μs wait time plus an additional 4.8 μs wait time for | ||||
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| a total of 9.6 μs. Note, however, that the average wait time per host | ||||
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| cycle in this case will still be 4.8 μs. | ||||
2 | INITDN | 0 |
| Initialization Done. When set to a 0, this bit enables the pull up and | ||||
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| pull down devices that are attached to the various | ||||
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| pins. When set to a 1, the pull up and pull down devices are | ||||
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| disabled, reducing standby current consumption to the minimum | ||||
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| possible level. |
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1 | TCR Mask | 0 |
| TCR Mask. When set to a 1, writes to TCR13, TCR14, and TCR15 | ||||
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| are ignored. This bit is provided as a security measure against acci- | ||||
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| dental reprogramming of network interface pin function by poorly | ||||
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| directed system accesses which could cause | ||||
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| nections to become established. | ||||
0 | STSCHGD | 0 |
| STSCHG Data. If the STSCHGFN bit of TCR15 has been set to a 1, | ||||
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| and the WAKEUP bit of the PCMCIA CCSR is set to a 1, then this bit | ||||
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| may be written with a 1 and writing a 0 to this bit has no effect. If the | ||||
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| STSCHGFN bit of TCR15 has been set to a 1, then STSCHGD is | ||||
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| reset to a 0 automatically whenever the WAKEUP bit of the | ||||
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84 |
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| Am79C930 |
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