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CONFIGURATION REGISTER INDEX: | 18h | |||
Bit | Name | Reset Value | Description | |
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7:6 | Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | |
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| undefined data. | |
5:0 | SS[5:0] | 00h | RSSI Sample Start. The value in this register is used to determine | |
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| when to capture a sample of the RSSI input for A/D conversion dur- | |
ing antenna diversity operation. The register value is a measure of the time of RSSI sample relative to the end of the current antenna dwell time (i.e., SS=03h implies that the RSSI sample will be con- verted at 3 μs before the current antenna dwell time ends).
The resolution of the RSSI sample timer is equal to 20 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 0 and is equal to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 μ. With CLKIN=20 MHz and CLKGT20 = 0, a value of SS[5:0] = 00100 means that the RSSI sample will be taken 4 μ before the next antenna switch event occurs. A register value of 0 means that no RSSI samples will be taken.
The time value represented by the bits in SS[5:0] must be less than the time value of the bits in the ADT[5:0] field of TCR4 minus the time value of the bits of the A2DT[3:0] field of TCR25 minus 9 CLKIN periods (18 CLKIN periods if CLKGT20=1).
TCR25: RSSI Configuration
This register is the RSSI Configuration register. This register is used to setup some A/D converter parameters.
CONFIGURATION REGISTER INDEX: | 19h | |||
Bit | Name | Reset Value | Description | |
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7 | UXA2DST | 0 | Use external A/D conversion Start signal. When UXA2DST is set to | |
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| 0, then the A/D conversion process starts when the Antenna Dwell | |
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| timer reaches the value programmed in the SS bits of TCR24. | |
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| When UXA2DST is set to 1, then an external stimulus from the | |
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| USER6/IRQ5/EXTA2DST pin is required to begin each A/D conver- | |
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| sion cycle. Rising edges of USER6/IRQ5/EXTA2DST initiate new | |
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| conversion cycles. A/D sample and conversion timing will proceed | |
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| as programmed in the TCR25 register A2DT field. | |
6 | ENEXT | 0 | Enable External. Setting ENEXT to a 1 enables the external A/D | |
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| mode of the Am79C930 device, allowing the Am79C930 device to | |
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| use the digital values supplied by an external A/D converter in CCA | |
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| and antenna diversity decisions. ENEXT is used in conjunction with | |
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| ENSAR (TCR25[5]) and ADDA (TIR26[2]) to configure the | |
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| Am79C930 device A/D mode according to the table listed in section | |
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| RSSI A/D Unit. | |
5 | ENSAR | 0 | Enable SAR. Setting ENSAR to a 1 enables the SAR[6:0] pins to | |
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| drive as outputs. ENSAR is used in conjunction with ENINT | |
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| (TCR25[6]) and ADDA (TIR26[2]) to configure the Am79C930 de- | |
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| vice A/D mode according to the table listed in the RSSI A/D unit de- | |
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| scription of in section RSSI A/D Unit. | |
4 | Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | |
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| undefined data. | |
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118 |
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| Am79C930 | |
