
P R E L I M I N A R Y | AMD |
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MIR8: Flash Wait States
This register gives the Flash Wait states.
Bit | Name | Reset Value |
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7:4 | Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | ||||
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| undefined data. |
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3 | HOSTALLOW | 1 |
| When this bit equals 1, then the host can access memory; if 0, then | |||
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| the host access is blocked completely | |||
2 | Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | ||||
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| undefined data. |
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1:0 | FLASHWAIT[1:0] | 11b |
| These bits must be set equal to or greater than the number of wait | |||
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| states that are generated internally in the 80188 core as defined by | |||
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| the programming of the R1 and R0 bits of the 80188 UMCS register. | |||
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| Wait states programmed into FLASHWAIT will cause wait states to | |||
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| be inserted into 80188 access to Flash and system accesses to | |||
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| Flash. Each wait state added to a Flash access is equivalent to two | |||
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| CLKIN periods. These bits are interpreted as follows: | |||
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| Number Of Wait |
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| States Used By |
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| Arbitration Logic For |
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| FLASHWAIT[1:0] | Flash Accesses |
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| 11 | 3 |
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| 10 | 2 |
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| 01 | 1 |
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| 00 | 0 |
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MIR9: TCR Mask STSCHG Data
This register contains TCR Mask, STSCHG Data, and
SRAM Wait States.
Bit | Name | Reset Value | Description |
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7 | CLKGT20 | 1 | CLKIN input is greater than 20 MHz. This bit must be set to a 1 by | ||
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| the 80188 code whenever the Am79C930 device is operating in a | ||
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| system that uses a source for the CLKIN input that is greater than | ||
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| 20 MHz in frequency. This information is needed in order to insure | ||
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| that the TAI section of the Am79C930 device is not pushed beyond | ||
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| design limits. Specifically, when CLKGT20 is set to 1, then the | ||
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| CLKIN signal is divided by 2 before being fed to the TAI section. | ||
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| CLKGT20 is also used to calibrate the time delay generated by the | ||
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| HOSTLONGWAIT counter. Specifically, if CLKGT20 = 1, then the | ||
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| number of CLKIN cycles that are counted for a system access | ||
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| WAIT period is 192 CLKIN periods; if CLKGT20 = 0, then the num- | ||
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| ber of CLKIN cycles that are counted for a system access WAIT pe- | ||
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| riod is 96 CLKIN periods. This time adjustment is needed in order to | ||
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| avoid creating a PCMCIA WAIT signal that exceeds the 12.1 μs | ||
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| limit indicated in the PCMCIA specification. |
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| If the source for the CLKIN input is a 20 MHz or slower clock signal, | ||
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| then this bit should remain reset at 0. |
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| The CLKGT20 bit has an effect on the network data rate. See the | ||
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| table in the Data Rate bit section in TCR30[2:0]. |
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| Am79C930 | 83 |