TCR31 Device Revision, 1Fh Description, Am79C930 123 | AMD specs

P R E L I M I N A R Y	AMD

2:0

DR[2:0]

001b

TCR31: Device Revision

This register is the Device Revision register.

CONFIGURATION REGISTER INDEX:

Bit

Name

Reset Value

then a 16-bit deep serial FIFO is inserted into the TX data path. This FIFO allows for some mismatch to be tolerated in the clock rates between the Am79C930 internal transmit clock and the external TXC clock that is connected to the TXC input. Because of this inter- nal FIFO, the appearance of transmit data from the setting of the TXS bit in TIR8 will be delayed by 8 bit times whenever the TXCIN bit has the value of 1.

The control of the function of the TXC pin is described in the Multi- Function Pin section.

Data Rate. The value in this register determines the data rate for the network. The TXC output pin will be affected. The following inter- pretations have been assigned to these bits:

DR[2:0]	CLKGT20	Network
TCR30[2:0]	MIR9[7]	Data Rate

000	0	reserved
001	0	fCLKIN÷20
010	0	fCLKIN÷40
011	0	fCLKIN÷80
100	0	reserved
101	0	fCLKIN÷200
110	0	fCLKIN÷2000
111	0	reserved
000	1	fCLKIN÷20
001	1	fCLKIN÷40
010	1	fCLKIN÷80
011	1	fCLKIN÷160
100	1	reserved
101	1	fCLKIN÷400
110	1	fCLKIN÷4000
111	1	reserved

The Data Rate bits are used together with the CLKGT20 bit to con- trol clock divider circuits in the DPLL section of the TAI and in the Transmit State machine section of the TAI. Specifically, the DPLL clock source will always be set at a rate of 20 times the desired Net- work Data rate in order to provide the appropriate amount of over- sampling to insure proper DPLL tracking of the incoming signal. The Transmit State machine section of the TAI logic will receive a divided clock that is equal to the desired Network Data Rate.

Note that if the CLKIN frequency is greater than 20 MHz, then the CLKGT20 bit must be set to 1.

1Fh

Description

7–0	REV[7:0]	01h	Revision Number. The value in this field contains the revision num-
			ber for the current device. The lowest revision number is 01h.

			Am79C930	123

Image 123

AMD manual TCR31 Device Revision, 1Fh Description, Am79C930 123

Contents

Am79C930 Speed Optional ProcessingOperating Conditions Package Type Rxdata Reset PcmciaJtag Trst TMS/T3 Adref INT1 IreqSIR0 MIR0 MIR1 SIR1 MIR15 SIR7 Srdy MUX IRQTIR0 TCR0 Fifo TIR31 TCR31 Table of Contents E L I M I N a R Y AMD TX Fifo RX FifoTAP FSM Register Descriptions TIR31 Test 126 Absolute Maximum Ratings AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Txpe TP1 Lfpe PTS1Hfpe PTS1 TP1, PTS1 Name Type LoadName Type Size of Pullup Size of Pulldown DRQ0 Txcmd Ieee Memr Reset LNK ACT CLK20 Test PwrdwnIeee Sddata Bale ISA Plug and Play Connection Diagram SD2 SD4 SD7SD6 SD5 TCK Adref SD5 Vsst ResetSA1 ACT SDSEL2 ADIN1 PTS3/OD2 SD7-SD0 ISA Plug and Play PIN Summary Pcmcia Pins with Internal Pull Up or Pull Down DevicesConfiguration Pins PIN Descriptions Input/Output Host System Interface PinsA14-0 D7-0 Iochrdy ResetAEN Bale MA16-0 IRQ4,5,9-12MD7-0 RXC ClkinPwrdwn Rxcin Rxdata HfclkLfclk Llocke Sddata USER7Adref Sdclk VDD5 TCKAvss TDI VDDU2 VSSVDDU1 VSSU1 Pin 45 STSCHG/BALE Pin 1 USER2/LA19Pin 2 USER3/SA16 Pin 3 USER4/LA17 Pin 92 USER7/IRQ11 Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 94 RXC/IRQ10/EXTA2DST Pin 95 USER6/IRQ5/EXTSDFPin 96 USER5/IRQ4/EXTCHBSY Pin 100 LNK Pin 98 ACT Pin 105 SDSEL2 Pin 101 SdclkPin 102 Sddata Pin 103 SDSEL3 Pin 122 Rxpe Pin 115 TXCPin 118 Lfpe Pin 120 Hfpe Pin 132 Antslt Pin 126 TxcmdPin 129 Txpe Pin 131 Txmod Pin 142 TXCMD/LA21 Pin 143 TXDATA/LA20Pin 144 LLOCKE/SA15 Bus Interface Unit Functional DescriptionBasic Functions Detailed Functions E L I M I N a R Y AMD AMD E L I M I N a R Y Memory Interface EmbeddedMedium Allocation AMD E L I M I N a R Y Flash Memory Management Transceiver Attachment Interface Unit ManagementBus Interface Unit Interaction Transceiver Attachment Interface Unit TX Power Ramp Control Tbclk = Tsclk X Pin Timing Reference Name When RCEN=0 When RCEN=1 RX Data Parallelization TX CRC GenerationTX Status Start of Frame Delimiter Detection RX Status Reporting Bit OrderingRssi A/D Unit Adda Enext Ensar UXA2DST Physical Header AccommodationDC Bias Control Baud Determination Logic Clear Channel Assessment Logic Rssi = Rssi Current CCA result is reported in the Chbsy bit of TIR26Automatic Antenna Diversity Logic Ubdcs Urssi Ieee 1149.1 Test Access Port Interface TXC As InputUbdsd Urssi Stpen Instruction Register and Decoding Logic Power Down FunctionBoundary Scan Circuit Supported Instructions E L I M I N a R Y AMD Applicability to Ieee 802.11 Power Down Modes Software AccessAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Resource Requirements Description of Reserved Use Am79C930 Device Pcmcia Mode Common Memory Restricted SpacePcmcia Address Size Physical Memory SIR153 XXX Am79C930 Device Pcmcia Mode Attribute Memory Map Pcmcia Address Attribute Memory Am79C930 Device Pcmcia Mode I/O MAP ISA Plug and Play Mode ResourcesPcmcia ISA Address in Memory SIR153 Size of Space Physical Memory Am79C930 Device ISA Plug And Play Mode Memory MapKbytes of memory Memory Range Memory Size ISA Address Size Physical Memory AMD E L I M I N a R Y Resource Name Am79C930 Device ISA Plug And Play Mode I/O MAPPhysical ISA SIR1 Readdata Port Name ISA Ieee P996 I/O Address AccessAddress Writedata Address ISA Plug and Play Plug and Play Port Register Name MAC Firmware Resources Physical Location of Memory Active INT0 TAI INT1 BIU Interrupt Channel Allocation in the 80188 CoreAddress Active Size Interrupt Channel Interrupt Source Loopback Operation Reset MethodsReset Pin DMA Channel Allocation In The 80188 Core Coreset SIR06 ISA PnP Reset Register DescriptionsSres TIR05 System Interface Registers SIR space Bit Name Reset Value Description SIR0 General Configuration Register GCR SIR1 Bank Switching Select Register BSS SIR3 Local Memory Address Register 148 LMA Bit Name Reset Value Description IODPA70MD70 during system interface accesses to Flash and Sram SIR2 Local Memory Address Register 70 LMA MAC Interface Registers MIR Space SIR5 I/O Data Port B IodpbMIR0 Processor Interface Register PIR MIR2 Power Down Length Count 70 Pdlc MIR1 Power Up Clock Time 30 Puct MIR5 Free Count 70 Fcnt MIR3 Power Down Length Count 158 PdlcMIR4 Power Down Length Count 2216 Pdlc Permarest MIR9 TCR Mask Stschg Data MIR8 Flash Wait StatesHostallow FLASHWAIT10 Stschgd SRAMWAIT10Hostlongwait Initdn Undefined data MIR10 ReservedThis register is reserved Reserved. Must be written as a 0. Reads of this bit produce Transceiver Attachment Interface Registers TIR Space TIR Register Name TIRSIR110 ISA Plug Core Play SIR110 Core TIR1 Network Status TIR0 Network Control TIR2 Serial Device Antsw TIR3 Fast Serial Port ControlTIR4 Interrupt Register Chbsyc TIR5 Interrupt Register TIR7 Interrupt Unmask Register TIR6 Interrupt Unmask Register TIR8 Transmit Control Txbsy TIR9 Transmit StatusTxcrc Txsdd TIR11 Transmit Sequence Control TIR12 Byte Count Register LSB TIR13 Byte Count Register MSBTIR14 Byte Count Limit LSB TIR15 Byte Count Limit MSB TIR16 Receiver ControlTIR17 Receive Status Register TIR20 CRC32 Correct Byte Count LSB RxbsyTIR18 RX Fifo Data Register TIR19 Reserved TIR21 CRC32 Correct Byte Count MSB TIR22 CRC8 Correct Byte Count LSBTIR23 CRC8 Correct Byte Count MSB TIR24 TCR Index Register TIR25 Configuration Data PortBit Name Reset Value Description CD70 By the current setting of the Configuration Index Register TIR27 Serial Approximation Register AddaSrcs Strtc TIR30 Test Dummy Register Bit Name Reset ValueTIR28 Rssi Lower Limit TIR29 User Pin Data TAI Configuration Register Space TCR TCR0 Network ConfigurationThese bit must be set to 0. Do not write to this register TCR1 Transmit Configuration 01h Bit Name Reset Value DescriptionAm79C930 105 03h TCR2 Clock RecoveryTCR3 Receive Configuration 02h 05h TCR4 Antenna Diversity Timer04h TCR5 TX Ramp Up Timing 07h TCR6 TX Ramp Down Timing06h TCR7 Pin Data a Txdatald U1INTCNTTxcmdt Antsltld 08h Bit Name Reset Value Description SDLT70 00hBit Name Reset Value Description SDLT158 00h TCR8 Start Delimiter LSB 0Ch TCR11 Interrupt Register0Bh TCR12 Interrupt Unmask Register 0Eh TCR13 Pin Configuration aTCR14 Pin Configuration B 0Dh TCR15 Pin Configuration C 0FhAm79C930 113 10h ActenStschgfn TCR16 Baud Detect Start TCR18 Baud Detect Upper Limit 11h Bit Name Reset Value Description12h Bit Name Reset Value Description Undefined data BDLLT50 TCR20 Baud Detect Accept Count for Stop Diversity TCR19 Baud Detect Accept Count for Carrier Sense13h BDCS50 TCR23 Baud Detect Fail Count 15h Bit Name Reset Value Description BDRN30TCR22 Baud Detect Accept Count 16h 19h TCR25 Rssi Configuration18h SS50 00h CACT=TIR277 Analog-to-Digital State Machine Timing Am79C930 119 TCR26 Reserved 1Ah1Bh TCR28 Clear Channel Assessment Configuration 1Ch Bit Name Reset Value DescriptionAm79C930 121 TCR29 Reserved 1Dh1Eh TCR31 Device Revision 1Fh DescriptionAm79C930 123 Pcmcia CCR Registers and Pcmcia CIS Space Pcmcia Configuration Option RegisterSreset Pcmcia Card Configuration and Status Register Am79C930 125 Vice actually enters the power down mode InterruptTil the interrupt has been serviced not pulse generated Pcmcia Card Information Structure CIS Commercial C Devices DC CharacteristicsAm79C930 DC Characteristics Absolute Maximum Ratings Operating Ranges DC Characteristics Am79C930 DC Characteristics Am79C930 127Parameter Description Test Conditions Min Max To 3.6 Temperature TA C to + 70C Supply VoltagesAbsolute Maximum Ratings VDDP, VDD5 Am79C930 129 130 Ieee 1149.1 DC Characteristics 5.0 and 3.3 Pcmcia Memory Read Access Am79C930 131Unit 132 Pcmcia Memory Write Access Am79C930 133 Pcmcia I/O Read Access 134 Pcmcia I/O Write Access Am79C930 135 136 ISA Access Am79C930 137 Memory BUS Read Access 138 Memory BUS Write Access Am79C930 139 140 Am79C930 141 AC Characteristics TAI Interface Absolute Maximum Ratings TAI Interface AC Characteristics Max Unit142 Am79C930 143 144 Am79C930 145 146 Clkin ↓ ANALOG-TO-DIGITAL A/D Converter Characteristics Am79C930 147TCK − Din Timing WaveformsPcmcia Bus Interface Waveforms REG Pcmcia I/O Read Access Timing Diagram 150 ISA Bus Interface Waveforms Clkin Clkout Memory Bus Interface Waveforms 152 Clock Waveforms TAI Waveforms ICORCO 154 Programmable Interface Waveforms Ieee 1149.1 Interface Waveforms Am79C930 155TDI, TMS AC Test Reference Waveforms Pcmcia AC Test Reference Waveform156 V Non-PCMCIA AC Test Reference Waveform NON-PCMCIA AC Test Reference Waveform Physical Dimensions PQT144 Pin Thin Quad Flat Pack measured in millimeters158 Typical Am79C930 System Application Device Configuration Frame Reception Frame Transmission Trademarks