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| P R E L I M I N A R Y | AMD | ||
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TIR12: Byte Count Register LSB |
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This register is the Byte count register LSB. This register | register; access by software is not needed for | |||||
contains the lower 8 bits of the | normal operation. |
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receive and transmit messages. This is a working |
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Bit | Name | Reset Value | Description |
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7:0 | BC[7:0] | 00h | Byte Count. Lower eight bits of current byte count for both transmit | |||
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| and receive operations. During transmit operations, the byte count | |||
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| reflects the number of bytes that have been transmitted following | |||
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| the transmission of the Start of Frame Delimiter. CRC is not in- | |||
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| cluded in this count for TX. During receive operations, the byte | |||
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| count reflects the number of bytes that have been written into the | |||
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| RX FIFO. This total excludes Preamble and Start Of Frame | |||
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| Delimiter bytes, but includes any PHY field and CRC bytes. | |||
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| Write accesses to this register from the software will cause | |||
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| unexpected results. |
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TIR13: Byte Count Register MSB |
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This register is the Byte count register MSB. This regis- | register; access by software is not needed for | |||||
ter contains the upper 4 bits of the | normal operation. |
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receive | and transmit messages. This is a | working |
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Bit | Name | Reset Value | Description |
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Reserved | – | Reserved. Must be written as a 0. Reads of this bit produce | |
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| undefined data. |
BC[11:8] | 0h | Byte Count. Upper 4 bits of current byte count for both transmit and |
receive operations. During transmit operations, the byte count re- flects the number of bytes that have been transmitted following the transmission of the Start of Frame Delimiter. CRC is not included in this count for TX. During receive operations, the byte count reflects the number of bytes that have been written into the RX FIFO. This total excludes Preamble and Start Of Frame Delimiter bytes, but in- cludes any PHY field and CRC bytes. Write accesses to this regis- ter from the software will cause unexpected results.
TIR14: Byte Count Limit LSB
This register is the Byte Count Limit LSB register.
Bit | Name | Reset Value | Description | |
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BCLT[7:0] | 00h | Byte Count Limit. Lower eight bits of byte count limit for both trans- | ||
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| mit and receive operations, depending upon which operation is | |
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| currently occurring. During transmit operations, when the byte | |
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| count limit is reached, an interrupt to the 80188 controller will be | |
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| generated if the TXBCNT interrupt has been unmasked. During TX, | |
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| the byte counter counts all bytes beginning with the first byte after | |
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| the SFD field has been detected and does not count the CRC bytes | |
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| appended to the TX frame. During RX, when the byte count limit is | |
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| reached, an interrupt to the 80188 controller will be generated if the | |
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| RXBCNT interrupt has been unmasked. During RX, the byte | |
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| counter counts all bytes that follow the Start of Frame Delimiter. | |
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| Byte count limit has no effect on state machine or | |
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| FIFO operations. |
Am79C930 | 97 |