Programmable Interface Waveforms, 154 | AMD Am79C930 guide

AMD	P R E L I M I N A R Y

PROGRAMMABLE INTERFACE WAVEFORMS

CLKIN

CLKOUT (internal)

WAIT or

IOCHRDY

tu1

RCO**

(data change)

tu2

RCO**

(drive change)

tu3

RCO** (drive change)

20138B-20

**RCO = Register Controlled Output

Figure 14. Programmable Interface Timing Diagram

154

Am79C930

Image 154

AMD Am79C930 manual Programmable Interface Waveforms, 154

Contents

Am79C930 Package Type Optional ProcessingOperating Conditions Speed Adref Reset PcmciaJtag Trst TMS/T3 Rxdata Srdy IreqSIR0 MIR0 MIR1 SIR1 MIR15 SIR7 INT1 Fifo TIR31 TCR31 IRQTIR0 TCR0 MUX Table of Contents E L I M I N a R Y AMD RX Fifo TX FifoTAP FSM Register Descriptions TIR31 Test Absolute Maximum Ratings 126 AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style TP1, PTS1 Lfpe PTS1Hfpe PTS1 Txpe TP1 Load Name TypeName Type Size of Pullup Size of Pulldown Bale Reset LNK ACT CLK20 Test PwrdwnIeee Sddata DRQ0 Txcmd Ieee Memr ISA Plug and Play Connection Diagram SD5 SD7SD6 SD2 SD4 ACT SDSEL2 ADIN1 SD5 Vsst ResetSA1 TCK Adref SD7-SD0 PTS3/OD2 ISA Plug and Play PIN Summary PIN Descriptions Pins with Internal Pull Up or Pull Down DevicesConfiguration Pins Pcmcia D7-0 Host System Interface PinsA14-0 Input/Output Bale ResetAEN Iochrdy IRQ4,5,9-12 MA16-0MD7-0 Rxcin ClkinPwrdwn RXC Llocke HfclkLfclk Rxdata Sdclk USER7Adref Sddata TDI TCKAvss VDD5 VSSU1 VSSVDDU1 VDDU2 Pin 3 USER4/LA17 Pin 1 USER2/LA19Pin 2 USER3/SA16 Pin 45 STSCHG/BALE Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 92 USER7/IRQ11 Pin 95 USER6/IRQ5/EXTSDF Pin 94 RXC/IRQ10/EXTA2DSTPin 96 USER5/IRQ4/EXTCHBSY Pin 98 ACT Pin 100 LNK Pin 103 SDSEL3 Pin 101 SdclkPin 102 Sddata Pin 105 SDSEL2 Pin 120 Hfpe Pin 115 TXCPin 118 Lfpe Pin 122 Rxpe Pin 131 Txmod Pin 126 TxcmdPin 129 Txpe Pin 132 Antslt Pin 143 TXDATA/LA20 Pin 142 TXCMD/LA21Pin 144 LLOCKE/SA15 Detailed Functions Functional DescriptionBasic Functions Bus Interface Unit E L I M I N a R Y AMD AMD E L I M I N a R Y Embedded Memory InterfaceMedium Allocation AMD E L I M I N a R Y Transceiver Attachment Interface Unit Management Flash Memory ManagementBus Interface Unit Interaction TX Power Ramp Control Transceiver Attachment Interface Unit Pin Timing Reference Name When RCEN=0 When RCEN=1 Tbclk = Tsclk X Start of Frame Delimiter Detection TX CRC GenerationTX Status RX Data Parallelization Bit Ordering RX Status ReportingRssi A/D Unit Baud Determination Logic Physical Header AccommodationDC Bias Control Adda Enext Ensar UXA2DST Clear Channel Assessment Logic Ubdcs Urssi Current CCA result is reported in the Chbsy bit of TIR26Automatic Antenna Diversity Logic Rssi = Rssi TXC As Input Ieee 1149.1 Test Access Port InterfaceUbdsd Urssi Stpen Supported Instructions Power Down FunctionBoundary Scan Circuit Instruction Register and Decoding Logic E L I M I N a R Y AMD Software Access Applicability to Ieee 802.11 Power Down ModesAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Resource Requirements Am79C930 Device Pcmcia Mode Common Memory Map SIR153 Am79C930 Device Pcmcia Mode Common Memory Restricted SpacePcmcia Address Size Physical Memory Description of Reserved Use Am79C930 Device Pcmcia Mode Attribute Memory Map XXX Pcmcia Address Attribute Memory ISA Plug and Play Mode Resources Am79C930 Device Pcmcia Mode I/O MAPPcmcia Memory Range Memory Size Am79C930 Device ISA Plug And Play Mode Memory MapKbytes of memory ISA Address in Memory SIR153 Size of Space Physical Memory ISA Address Size Physical Memory AMD E L I M I N a R Y ISA SIR1 Am79C930 Device ISA Plug And Play Mode I/O MAPPhysical Resource Name Writedata Port Name ISA Ieee P996 I/O Address AccessAddress Readdata ISA Plug and Play Plug and Play Port Register Name Address MAC Firmware Resources Active Physical Location of Memory Interrupt Channel Interrupt Source Interrupt Channel Allocation in the 80188 CoreAddress Active Size INT0 TAI INT1 BIU DMA Channel Allocation In The 80188 Core Reset MethodsReset Pin Loopback Operation Coreset SIR06 Register Descriptions ISA PnP ResetSres TIR05 System Interface Registers SIR space SIR0 General Configuration Register GCR Bit Name Reset Value Description SIR1 Bank Switching Select Register BSS SIR2 Local Memory Address Register 70 LMA Bit Name Reset Value Description IODPA70MD70 during system interface accesses to Flash and Sram SIR3 Local Memory Address Register 148 LMA SIR5 I/O Data Port B Iodpb MAC Interface Registers MIR SpaceMIR0 Processor Interface Register PIR MIR1 Power Up Clock Time 30 Puct MIR2 Power Down Length Count 70 Pdlc Permarest MIR3 Power Down Length Count 158 PdlcMIR4 Power Down Length Count 2216 Pdlc MIR5 Free Count 70 Fcnt FLASHWAIT10 MIR8 Flash Wait StatesHostallow MIR9 TCR Mask Stschg Data Initdn SRAMWAIT10Hostlongwait Stschgd Reserved. Must be written as a 0. Reads of this bit produce MIR10 ReservedThis register is reserved Undefined data Transceiver Attachment Interface Registers TIR Space Play TIRSIR110 ISA Plug Core TIR Register Name SIR110 Core TIR0 Network Control TIR1 Network Status TIR2 Serial Device Chbsyc TIR3 Fast Serial Port ControlTIR4 Interrupt Register Antsw TIR5 Interrupt Register TIR6 Interrupt Unmask Register TIR7 Interrupt Unmask Register TIR8 Transmit Control Txsdd TIR9 Transmit StatusTxcrc Txbsy TIR11 Transmit Sequence Control TIR13 Byte Count Register MSB TIR12 Byte Count Register LSBTIR14 Byte Count Limit LSB TIR16 Receiver Control TIR15 Byte Count Limit MSBTIR17 Receive Status Register TIR19 Reserved RxbsyTIR18 RX Fifo Data Register TIR20 CRC32 Correct Byte Count LSB TIR22 CRC8 Correct Byte Count LSB TIR21 CRC32 Correct Byte Count MSBTIR23 CRC8 Correct Byte Count MSB By the current setting of the Configuration Index Register TIR25 Configuration Data PortBit Name Reset Value Description CD70 TIR24 TCR Index Register Strtc AddaSrcs TIR27 Serial Approximation Register TIR29 User Pin Data Bit Name Reset ValueTIR28 Rssi Lower Limit TIR30 Test Dummy Register TCR0 Network Configuration TAI Configuration Register Space TCRThese bit must be set to 0. Do not write to this register 01h Bit Name Reset Value Description TCR1 Transmit ConfigurationAm79C930 105 02h TCR2 Clock RecoveryTCR3 Receive Configuration 03h TCR5 TX Ramp Up Timing TCR4 Antenna Diversity Timer04h 05h TCR7 Pin Data a TCR6 TX Ramp Down Timing06h 07h Antsltld U1INTCNTTxcmdt Txdatald TCR8 Start Delimiter LSB Bit Name Reset Value Description SDLT70 00hBit Name Reset Value Description SDLT158 00h 08h TCR12 Interrupt Unmask Register TCR11 Interrupt Register0Bh 0Ch 0Dh TCR13 Pin Configuration aTCR14 Pin Configuration B 0Eh 0Fh TCR15 Pin Configuration CAm79C930 113 TCR16 Baud Detect Start ActenStschgfn 10h Undefined data BDLLT50 11h Bit Name Reset Value Description12h Bit Name Reset Value Description TCR18 Baud Detect Upper Limit BDCS50 TCR19 Baud Detect Accept Count for Carrier Sense13h TCR20 Baud Detect Accept Count for Stop Diversity 16h 15h Bit Name Reset Value Description BDRN30TCR22 Baud Detect Accept Count TCR23 Baud Detect Fail Count SS50 00h TCR25 Rssi Configuration18h 19h Analog-to-Digital State Machine Timing Am79C930 119 CACT=TIR277 1Ah TCR26 Reserved1Bh 1Ch Bit Name Reset Value Description TCR28 Clear Channel Assessment ConfigurationAm79C930 121 1Dh TCR29 Reserved1Eh 1Fh Description TCR31 Device RevisionAm79C930 123 Pcmcia Card Configuration and Status Register Pcmcia Configuration Option RegisterSreset Pcmcia CCR Registers and Pcmcia CIS Space Pcmcia Card Information Structure CIS Vice actually enters the power down mode InterruptTil the interrupt has been serviced not pulse generated Am79C930 125 Absolute Maximum Ratings Operating Ranges DC CharacteristicsAm79C930 DC Characteristics Commercial C Devices Am79C930 127 DC Characteristics Am79C930 DC CharacteristicsParameter Description Test Conditions Min Max VDDP, VDD5 Temperature TA C to + 70C Supply VoltagesAbsolute Maximum Ratings To 3.6 Am79C930 129 Ieee 1149.1 DC Characteristics 5.0 and 3.3 130 Am79C930 131 Pcmcia Memory Read AccessUnit Pcmcia Memory Write Access 132 Pcmcia I/O Read Access Am79C930 133 Pcmcia I/O Write Access 134 Am79C930 135 ISA Access 136 Memory BUS Read Access Am79C930 137 Memory BUS Write Access 138 Am79C930 139 140 AC Characteristics TAI Interface Absolute Maximum Ratings Am79C930 141 Max Unit TAI Interface AC Characteristics142 Am79C930 143 144 Am79C930 145 Clkin ↓ 146 Am79C930 147 ANALOG-TO-DIGITAL A/D Converter CharacteristicsTCK − REG Timing WaveformsPcmcia Bus Interface Waveforms Din Pcmcia I/O Read Access Timing Diagram ISA Bus Interface Waveforms 150 Memory Bus Interface Waveforms Clkin Clkout Clock Waveforms 152 ICO TAI WaveformsRCO Programmable Interface Waveforms 154 Am79C930 155 Ieee 1149.1 Interface WaveformsTDI, TMS Pcmcia AC Test Reference Waveform AC Test Reference Waveforms156 NON-PCMCIA AC Test Reference Waveform V Non-PCMCIA AC Test Reference Waveform PQT144 Pin Thin Quad Flat Pack measured in millimeters Physical Dimensions158 Device Configuration Typical Am79C930 System Application Frame Transmission Frame Reception Trademarks