AMD | P R E L I M I N A R Y |
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The sleep state machine is returned to its idle state (i.e., awake).
The memory bus arbitration state machine is re- turned to its idle state.
The following registers and state machines which are UNAFFECTED by assertion of the SWRESET bit of SIR0[7]:
SIR0[7] and all of SIR2[7:0] and SIR3[6:0] are unaf- fected by SWRESET.
TIR registers are unaffected by SWRESET.
TCR registers are unaffected by SWRESET.
TAI state machines are unaffected by SWRESET.
The 80188 controller is unaffected by SWRESET.
PCMCIA registers are unaffected by SWRESET.
ISA PnP registers are unaffected by SWRESET.
The ISA PnP state machine is unaffected by SWRESET.
It is generally recommended that the SWRESET bit of SIR0[7] should NOT be SET to a 1 unless the CORESET bit of SIR0[6] has first been set to a 1. This recommendation is to insure that the memory bus arbi- tration state machine is not reset while the 80188 em- bedded controller is executing an access. The proper sequence for using the SWRESET bit should be:
1.SET the CORESET bit SIR0[6] to a 1.
2.SET the SWRESET bit SIR0[7] to a 1.
3.RESET the SWRESET bit SIR0[7] to a 0.
4.RESET the CORESET bit SIR0[6] to a 0.
An option to this procedure is to first insure that the 80188 controller is in the HALT state before the SWRESET bit is asserted. However, note that the FLASHWAIT and SRAMWAIT values are reset by SWRESET; therefore, if 80188 operations are resumed after the SWRESET has been performed, the perform- ance of the 80188 may be affected.
The user may decide not to follow these recommenda- tions, but in such a case, it should be recognized that the 80188 may suffer from unpredictable behavior as a result.
CORESET (SIR0[6])
The CORESET bit of SIR0[6] can be used to reset the embedded controller and TAI sections of the Am79C930 device, along with a few locations in the MIR register space. When the CORESET bit is asserted, then the 80188 section of the Am79C930 device will be placed into reset, with behavior identical to that of a
standalone 80188 controller having its RESET pin as- serted. TAI section of the Am79C930 device will also be- come reset with all registers returning to their default states, as will a few bits in the MIR register set.
The following is a complete list of registers and state ma- chines that will become reset to default values with the assertion of the CORESET bit of SIR0[6]:
(Note that some register locations' default values are UNDEFINED):
All TIR registers.
All TCR registers.
MIR8[1:0] are reset to 11b.
MIR9[5:4] are reset to 11b.
All TAI state machines are reset by the assertion of CORESET.
The 80188 controller is held in RESET as long as the CORESET bit is held at a 1 level.
The following registers and state machines are UNAFFECTED by assertion of the CORESET bit of SIR0[6]:
The | ISA PnP state | machine | is | unaffected |
by CORESET. |
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The | sleep state | machine | is | unaffected |
by CORESET. |
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The memory bus arbitration state machine is unaf- fected by CORESET.
PCMCIA COR SRESET
The PCMCIA Configuration Option Register contains a reset bit in location [7] which is labeled SRESET. When SRESET is asserted, the entire Am79C930 device will become reset as though the RESET pin had been as- serted, except that the asynchronous logic which is used to perform PCMCIA register accesses is not reset.
The following is a complete list of registers and state ma- chines that will become reset to default values with the assertion of the COR SRESET bit of PCMCIA COR[7]:
(Note that some register locations' default values are UNDEFINED):
All PCMCIA registers, except COR[7].
All MIR registers.
All SIR registers, except SIR0[7], SIR2[7:0], and SIR3[6:0].
The memory bus arbitration state machine is re- turned to its idle state.
74 | Am79C930 |
