AMD Am79C930 - page 115

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115Am79C930

TCR17: Baud Detect Lower Limit

This register is the Baud Detect Lower Limit

CONFIGURATION REGISTER INDEX: 11h

Bit Name Reset Value Description

7–6 Reserved – Reserved. Must be written as a 0. Reads of this bit produce

undefined data.

5–0 BDLLT[5:0] 00h Baud Detect Lower Limit. This register is used to program the lower

limit for the Baud detection circuit. The lower limit defines the short-

est time between like transitions (i.e., rising edge to rising edge or

falling edge to falling edge) that is expected for a given baud rate. If

like transitions are separated by values below this limit, then the

baud detect test for that pair of like transitions will fail.

Note that the rising edge baud counter will begin counting from 0

and when it reaches a value of 29, the next increment will cause the

counter to wrap to a value of 10 decimal. The falling edge baud

counter operates in an identical manner. Therefore, rising edges

that are separated by 20, 40, 60, 80, etc. CLKIN periods (with

CLKGT20=0 each baud tick is one CLKIN period, with

CLKGT20=1, each baud tick is two CLKIN periods) will all yield a

rising edge baud counter value of 20. The same is true for the falling

edge baud counter. This information should be used to appropri-

ately program the Baud Detect Lower Limit register.

The resolution of the value in this register is the period of the CLKIN

signal when the CLKGT20 bit of MIR9 is set to 0 or twice the period

of the CLKIN signal when the CLKGT20 bit of MIR9 is set to 1. With

CLKIN = 20 MHz and CLKGT20=0, a value of 14h (=20 decimal)

represents the

nominal

pulse width value for 1 Mbit/s network data

rate operation.

TCR18: Baud Detect Upper Limit.

This register is the Baud Detect Upper Limit register.

CONFIGURATION REGISTER INDEX: 12h