AMD manual TCR11 Interrupt Register, 0Bh, TCR12 Interrupt Unmask Register, 0Ch, Am79C930 111

P R E L I M I N A R Y AMD

Delimiter may be used for start of frame recognition by appropriate settings of the SD[1:0] bits in the Network Configuration Register (TCR0). Start of Frame detection is performed on the bits in the or- der that they appear on the medium, with the SDLT LSB, bit 0, being checked against the first bit to arrive at the Am79C930 (RX case) or the first bit to leave the Am79C930 (Tx case) and continuing in that order.

TCR11: Interrupt Register 3

This register is the TAI Interrupt Register 3. Provides in- terrupt status information. Any interrupt bit may be cleared by writing a 1 to the bit location. Writing a 0 to a bit location has no effect on the bit value. An interrupt in

TCR11 will be signaled in TIR4 through the MOREINT bit when the associated unmask bit has been set in TCR12.

CONFIGURATION REGISTER INDEX:			0Bh
Bit	Name	Reset Value	Description
7:4	Reserved	–	Reserved. Must be written as a 0. Reads of these bits produce
			undefined data.
3	U1INT	0	USER1 Interrupt. When U1INT is set to 1, it indicates that a change
			of state has occurred at the USER1/IRQ12 pin. The change of state
			required to signal an interrupt on the U1INT bit is determined by the
			settings of the U1INTSC bits of TCR7[4:3]. This function may be
			disabled with an appropriate setting of the U1INTSC bits. A corre-
			sponding unmask bit for this interrupt source exists in TCR12.
2	RUNERR	1	Run Length Error. When RUNERR is set to a 1, it indicates that the
			total number of 1s during a received message exceeds the total
			number of 0s at any given time by 25, or that the total number of 0s
			in the message at any given time exceeds the number of 1s in the
			message by 27. This function may be disabled with the DISRNR bit
			of TCR27.
1	ATFO	0	Asynchronous Transmit FIFO Overflow. When ATFO is set to 1, it
			indicates that the asynchronous transmit FIFO has overflowed.
0	ATFU	0	Asynchronous Transmit FIFO Underflow. When ATFU is set to 1, it
			indicates that the asynchronous transmit FIFO has underflowed.

TCR12: Interrupt Unmask Register 3

This register is the Interrupt Unmask Register 3. Each bit in this register will unmask the corresponding

interrupt of the Interrupt Register 2 (TIR5) when the un- mask bit is set to 1.

CONFIGURATION REGISTER INDEX:			0Ch
Bit	Name	Reset Value	Description
7:4	Reserved	–	Reserved. Must be written as a 0. Reads of these bits produce
			undefined data.
3	U1INTU	0	USER1 Interrupt Unmask.
2	RUNERRU	0	RUNERR Interrupt Unmask.
1	ATFOU	0	Asynchronous Transmit FIFO Overflow Interrupt Unmask.
0	ATFUU	0	Asynchronous Transmit FIFO Underflow Interrupt Unmask.

Am79C930 111