U1INTCNT, Txcmdt, Antsltld, Txdatald, Am79C930 109 | AMD guide

			P R E L I M I N A R Y					AMD

				In addition, the USER5/IRQ4 pin may be used to produce interrupts
				to the 80188 embedded controller. This capability is controlled by
				the ENXCHBSY bit of TCR28 and the CHBSYCU bit of TIR5 and
				operates independently of the bits mentioned above.
				The control of the function of the USER5/IRQ4 pin is described in
				the Multi-Function Pin section.
4–3	U1INTCNT	00b	USER1 Interrupt control bits. The USER1/IRQ12 pin can be used
				to signal an interrupt to the 80188 embedded controller. The
				U1INTCNT bits have the following interpretation and operate inde-
				pendently of the operating mode of the Am79C930 device (i.e.,
				the U1INTCNT bits operate in both PCMCIA and ISA Plug and
				Play modes.):

							U1INT Bit
				U1INTCNT		USER1 Pin	(TCR11[3])
				TCR7[4:3]		Event	Result

				00		X	0 => interrupt
							disabled

				01		rising edge	1 => interrupt
							signaled

				10		falling edge	1 => interrupt
							signaled

				11		rising or	1 => interrupt
						falling edge	signaled

				Note that the USER1 pin function has no effect on the use of the
				USER1/IRQ12 pin as an interrupt signaling pin. If the
				USER1/IRQ12 pin is to be used as a 80188 controller interrupt
				source in the ISA Plug and Play mode, then it is imperative that the
				ISA Plug and Play resource data structure loaded into the accom-
				panying flash device as part of the Am79C930 device based design
				should not include IRQ12 as a choice of IRQ level for possible se-
				lection by the ISA Plug and Play configuration software. When this
				procedure is followed, then the system designer can be assured
				that the IRQ12 function will not be used by the Am79C930 device,
				and therefore, the USER1/IRQ12 pin will remain in the high-imped-
				ance state and will be available for connection to an interrupt gener-
				ating source in the design.
2	TXCMDT	0		TXCMD Data. The value written to the TXCMDT bit is used in some
				modes to determine the output value of the TXCMD/LA21 pin.
				Reads from TXCMDT always return the current value of the
				TXCMD/LA21 pin.
				The control of the function of the TXCMD/LA21 pin is described in
				the Multi-Function Pin section.
1	ANTSLTLD	1		ANTSLTL Data. The value that is written to this bit will be driven out
				to the ANTSLT pin of the Am79C930 device when the ANTSLTLFN
				bit of TCR30 has been set to a 1 and the ANTSLTLEN bit of TCR15
				has also been set to a 1 and the PCMCIA pin is set to 1. The value
				that is read from this bit represents the current value of the ANTSLT
				pin of the Am79C930 device.
				A complete description of the control of the function of the ANTSLT
				pin is described in the Multi-Function Pin section.
0	TXDATALD	1		TXDATAL Data. The value that is written to this bit will be driven out
				to the TXDATA pin of the Am79C930 device when the TXDATALFN
				bit of TCR30 has been set to a 1 and the TXDATALEN bit of TCR15

				Am79C930			109

Image 109

AMD manual U1INTCNT, Txcmdt, Antsltld, Txdatald, Am79C930 109

Contents

Am79C930 Operating Conditions Optional ProcessingPackage Type Speed Jtag Trst TMS/T3 Reset PcmciaAdref Rxdata SIR0 MIR0 MIR1 SIR1 MIR15 SIR7 IreqSrdy INT1 TIR0 TCR0 IRQFifo TIR31 TCR31 MUX Table of Contents E L I M I N a R Y AMD RX Fifo TX FifoTAP FSM Register Descriptions TIR31 Test 126 Absolute Maximum Ratings AMD E L I M I N a R Y Pcmcia Connection Diagram Pin No Pin Name Pin Name Pin No No. Pins Pin Name Pin Function Pin Style Hfpe PTS1 Lfpe PTS1TP1, PTS1 Txpe TP1 Load Name TypeName Type Size of Pullup Size of Pulldown Ieee Sddata Reset LNK ACT CLK20 Test PwrdwnBale DRQ0 Txcmd Ieee Memr ISA Plug and Play Connection Diagram SD6 SD7SD5 SD2 SD4 SA1 SD5 Vsst ResetACT SDSEL2 ADIN1 TCK Adref PTS3/OD2 SD7-SD0 ISA Plug and Play PIN Summary Configuration Pins Pins with Internal Pull Up or Pull Down DevicesPIN Descriptions Pcmcia A14-0 Host System Interface PinsD7-0 Input/Output AEN ResetBale Iochrdy IRQ4,5,9-12 MA16-0MD7-0 Pwrdwn ClkinRxcin RXC Lfclk HfclkLlocke Rxdata Adref USER7Sdclk Sddata Avss TCKTDI VDD5 VDDU1 VSSVSSU1 VDDU2 Pin 2 USER3/SA16 Pin 1 USER2/LA19Pin 3 USER4/LA17 Pin 45 STSCHG/BALE Pin 92 USER7/IRQ11 Pin 91 USER1/IRQ12/EXTCTS/EXINT188 Pin 95 USER6/IRQ5/EXTSDF Pin 94 RXC/IRQ10/EXTA2DSTPin 96 USER5/IRQ4/EXTCHBSY Pin 100 LNK Pin 98 ACT Pin 102 Sddata Pin 101 SdclkPin 103 SDSEL3 Pin 105 SDSEL2 Pin 118 Lfpe Pin 115 TXCPin 120 Hfpe Pin 122 Rxpe Pin 129 Txpe Pin 126 TxcmdPin 131 Txmod Pin 132 Antslt Pin 143 TXDATA/LA20 Pin 142 TXCMD/LA21Pin 144 LLOCKE/SA15 Basic Functions Functional DescriptionDetailed Functions Bus Interface Unit E L I M I N a R Y AMD AMD E L I M I N a R Y Embedded Memory InterfaceMedium Allocation AMD E L I M I N a R Y Transceiver Attachment Interface Unit Management Flash Memory ManagementBus Interface Unit Interaction Transceiver Attachment Interface Unit TX Power Ramp Control Tbclk = Tsclk X Pin Timing Reference Name When RCEN=0 When RCEN=1 TX Status TX CRC GenerationStart of Frame Delimiter Detection RX Data Parallelization Bit Ordering RX Status ReportingRssi A/D Unit DC Bias Control Physical Header AccommodationBaud Determination Logic Adda Enext Ensar UXA2DST Clear Channel Assessment Logic Automatic Antenna Diversity Logic Current CCA result is reported in the Chbsy bit of TIR26Ubdcs Urssi Rssi = Rssi TXC As Input Ieee 1149.1 Test Access Port InterfaceUbdsd Urssi Stpen Boundary Scan Circuit Power Down FunctionSupported Instructions Instruction Register and Decoding Logic E L I M I N a R Y AMD Software Access Applicability to Ieee 802.11 Power Down ModesAm79C930 System Interface Resources Am79C930 Device Pcmcia Mode Common Memory Map Am79C930 Device Pcmcia Mode Resource Requirements Pcmcia Address Size Physical Memory Am79C930 Device Pcmcia Mode Common Memory Restricted SpaceSIR153 Description of Reserved Use XXX Am79C930 Device Pcmcia Mode Attribute Memory Map Pcmcia Address Attribute Memory ISA Plug and Play Mode Resources Am79C930 Device Pcmcia Mode I/O MAPPcmcia Kbytes of memory Am79C930 Device ISA Plug And Play Mode Memory MapMemory Range Memory Size ISA Address in Memory SIR153 Size of Space Physical Memory ISA Address Size Physical Memory AMD E L I M I N a R Y Physical Am79C930 Device ISA Plug And Play Mode I/O MAPISA SIR1 Resource Name Address Port Name ISA Ieee P996 I/O Address AccessWritedata Readdata Address ISA Plug and Play Plug and Play Port Register Name MAC Firmware Resources Physical Location of Memory Active Address Active Size Interrupt Channel Allocation in the 80188 CoreInterrupt Channel Interrupt Source INT0 TAI INT1 BIU Reset Pin Reset MethodsDMA Channel Allocation In The 80188 Core Loopback Operation Coreset SIR06 Register Descriptions ISA PnP ResetSres TIR05 System Interface Registers SIR space Bit Name Reset Value Description SIR0 General Configuration Register GCR SIR1 Bank Switching Select Register BSS MD70 during system interface accesses to Flash and Sram Bit Name Reset Value Description IODPA70SIR2 Local Memory Address Register 70 LMA SIR3 Local Memory Address Register 148 LMA SIR5 I/O Data Port B Iodpb MAC Interface Registers MIR SpaceMIR0 Processor Interface Register PIR MIR2 Power Down Length Count 70 Pdlc MIR1 Power Up Clock Time 30 Puct MIR4 Power Down Length Count 2216 Pdlc MIR3 Power Down Length Count 158 PdlcPermarest MIR5 Free Count 70 Fcnt Hostallow MIR8 Flash Wait StatesFLASHWAIT10 MIR9 TCR Mask Stschg Data Hostlongwait SRAMWAIT10Initdn Stschgd This register is reserved MIR10 ReservedReserved. Must be written as a 0. Reads of this bit produce Undefined data Transceiver Attachment Interface Registers TIR Space SIR110 ISA Plug Core TIRPlay TIR Register Name SIR110 Core TIR1 Network Status TIR0 Network Control TIR2 Serial Device TIR4 Interrupt Register TIR3 Fast Serial Port ControlChbsyc Antsw TIR5 Interrupt Register TIR7 Interrupt Unmask Register TIR6 Interrupt Unmask Register TIR8 Transmit Control Txcrc TIR9 Transmit StatusTxsdd Txbsy TIR11 Transmit Sequence Control TIR13 Byte Count Register MSB TIR12 Byte Count Register LSBTIR14 Byte Count Limit LSB TIR16 Receiver Control TIR15 Byte Count Limit MSBTIR17 Receive Status Register TIR18 RX Fifo Data Register RxbsyTIR19 Reserved TIR20 CRC32 Correct Byte Count LSB TIR22 CRC8 Correct Byte Count LSB TIR21 CRC32 Correct Byte Count MSBTIR23 CRC8 Correct Byte Count MSB Bit Name Reset Value Description CD70 TIR25 Configuration Data PortBy the current setting of the Configuration Index Register TIR24 TCR Index Register Srcs AddaStrtc TIR27 Serial Approximation Register TIR28 Rssi Lower Limit Bit Name Reset ValueTIR29 User Pin Data TIR30 Test Dummy Register TCR0 Network Configuration TAI Configuration Register Space TCRThese bit must be set to 0. Do not write to this register 01h Bit Name Reset Value Description TCR1 Transmit ConfigurationAm79C930 105 TCR3 Receive Configuration TCR2 Clock Recovery02h 03h 04h TCR4 Antenna Diversity TimerTCR5 TX Ramp Up Timing 05h 06h TCR6 TX Ramp Down TimingTCR7 Pin Data a 07h Txcmdt U1INTCNTAntsltld Txdatald Bit Name Reset Value Description SDLT158 00h Bit Name Reset Value Description SDLT70 00hTCR8 Start Delimiter LSB 08h 0Bh TCR11 Interrupt RegisterTCR12 Interrupt Unmask Register 0Ch TCR14 Pin Configuration B TCR13 Pin Configuration a0Dh 0Eh 0Fh TCR15 Pin Configuration CAm79C930 113 Stschgfn ActenTCR16 Baud Detect Start 10h 12h Bit Name Reset Value Description 11h Bit Name Reset Value DescriptionUndefined data BDLLT50 TCR18 Baud Detect Upper Limit 13h TCR19 Baud Detect Accept Count for Carrier SenseBDCS50 TCR20 Baud Detect Accept Count for Stop Diversity TCR22 Baud Detect Accept Count 15h Bit Name Reset Value Description BDRN3016h TCR23 Baud Detect Fail Count 18h TCR25 Rssi ConfigurationSS50 00h 19h CACT=TIR277 Analog-to-Digital State Machine Timing Am79C930 119 1Ah TCR26 Reserved1Bh 1Ch Bit Name Reset Value Description TCR28 Clear Channel Assessment ConfigurationAm79C930 121 1Dh TCR29 Reserved1Eh 1Fh Description TCR31 Device RevisionAm79C930 123 Sreset Pcmcia Configuration Option RegisterPcmcia Card Configuration and Status Register Pcmcia CCR Registers and Pcmcia CIS Space Til the interrupt has been serviced not pulse generated Vice actually enters the power down mode InterruptPcmcia Card Information Structure CIS Am79C930 125 Am79C930 DC Characteristics DC CharacteristicsAbsolute Maximum Ratings Operating Ranges Commercial C Devices Am79C930 127 DC Characteristics Am79C930 DC CharacteristicsParameter Description Test Conditions Min Max Absolute Maximum Ratings Temperature TA C to + 70C Supply VoltagesVDDP, VDD5 To 3.6 Am79C930 129 130 Ieee 1149.1 DC Characteristics 5.0 and 3.3 Am79C930 131 Pcmcia Memory Read AccessUnit 132 Pcmcia Memory Write Access Am79C930 133 Pcmcia I/O Read Access 134 Pcmcia I/O Write Access Am79C930 135 136 ISA Access Am79C930 137 Memory BUS Read Access 138 Memory BUS Write Access Am79C930 139 140 Am79C930 141 AC Characteristics TAI Interface Absolute Maximum Ratings Max Unit TAI Interface AC Characteristics142 Am79C930 143 144 Am79C930 145 146 Clkin ↓ Am79C930 147 ANALOG-TO-DIGITAL A/D Converter CharacteristicsTCK − Pcmcia Bus Interface Waveforms Timing WaveformsREG Din Pcmcia I/O Read Access Timing Diagram 150 ISA Bus Interface Waveforms Clkin Clkout Memory Bus Interface Waveforms 152 Clock Waveforms ICO TAI WaveformsRCO 154 Programmable Interface Waveforms Am79C930 155 Ieee 1149.1 Interface WaveformsTDI, TMS Pcmcia AC Test Reference Waveform AC Test Reference Waveforms156 V Non-PCMCIA AC Test Reference Waveform NON-PCMCIA AC Test Reference Waveform PQT144 Pin Thin Quad Flat Pack measured in millimeters Physical Dimensions158 Typical Am79C930 System Application Device Configuration Frame Reception Frame Transmission Trademarks