AMD Am79C930 manual Tck, Avss, Tdi, VDD5, Tdo, Tms, Vddt, Avdd, Vsst, Vcc

AMD	P R E L I M I N A R Y
IEEE 1149.1 Test Access Port Pins		supply voltage. Special attention should be paid to the
TCK		printed circuit board layout to avoid excessive noise on
		the AVDD line.
Test Clock	Input
TCK is the clock input for the boundary scan test mode		AVSS
operation. TCK frequency may be as high as 10 MHz.		Analog Ground (1 Pin)	Ground
TCK does not have an internal pull-up resistor and must		There is one analog ground pin. This ground pin pro-
be connected to a valid TTL or CMOS level at all times.
		vides ground reference to the analog section of the
TCK must not be left unconnected.
		Am79C930 device. This pin must always be connected
TDI		to a ground supply. Special attention should be paid to
		the printed circuit board layout to avoid excessive noise
Test Data Input	Input
		on the AVSS line.
TDI is the test data input path to the Am79C930 device.
		VDD5
If left unconnected, this pin has a default value of HIGH.
TDO		A/D Power (1 Pins)	Power
		There is one A/D power supply pin. This pin provides
Test Data Output	Output
		power to the A to D converter circuit. This pin must
TDO is the test data output path from the Am79C930 de-
		always be connected to a 5 V supply unless the A/D
vice. TDO is tri-stated when the JTAG port is inactive.
		function of the device is not required. If the A/D function
TMS		of the device is not required, then this pin may be con-
		nected to either a 5 V supply or to a 3.3 V supply. How-
Test Mode Select	Input
		ever, all analog power pins (AVDD and VDD5) must be
TMS is a serial input bit stream is used to define the spe-
		connected to the same supply voltage. Special attention
cific boundary scan test to be executed. If left uncon-		should be paid to the printed circuit board layout to avoid
nected, this pin has a default value of HIGH.		excessive noise on the VDD5 line.
TRST		Digital Power Supply Pins
Test Reset	Input	VDDT
When asserted, TRST will asynchronously reset the
		Transceiver Power (2 Pins)	Power
IEEE 1149.1 state. The reset state of the IEEE 1149.1		There are two transceiver interface power supply pins.
state machine is FFh.
		These pins provide power to the transceiver interface
Test Pin		buffers and drivers on pins 98 through 133. These pins
TEST		may be connected to either a 5.0 V supply or a 3.3 V sup-
		ply, but both of these pins must be connected to the
Test	Input
		same supply voltage.

The TEST pin should be tied HIGH and is reserved for internal factory test only.

Power Supply Pins

Analog Power Supply Pins

AVDD

Analog Power (1 Pin) Power

There is one analog 5 V supply pin. This supply pin pro- vides power to the analog section of the Am79C930 de- vice. This pin must always be connected to 5 V, unless the A/D function of the device is not required. If the A/D function of the device is not required, then this pin may be connected to either a 5 V supply or to a 3.3 V supply. Note: A/D must be disabled. However, all analog power pins (AVDD and VDD5) must be connected to the same

VSST

Transceiver Ground (4 Pins) Ground

There are four transceiver interface ground pins. These pins provide ground reference to the transceiver interface buffers and drivers on pins 98 through 133. In both 5 V and 3 V systems, these pins should be con- nected to a ground supply.

VCC

Core Logic Power (2 Pins) Power

There are two core logic power supply pins. These pins provide power to the core logic and must always be less than or equal to VDDT, VDDU1, VDDU2, VDDP, and VDDM.

32 Am79C930