Appendix
CPU | DIMM | 4 CPUMEMRs | 6 CPUMEMRs | 8 CPUMEMRs | IOH | |||||||||
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1B | 1A | 2B | 2A | 1B | 1A | 2B | 2A | 1B | 1A | 2B | 2A | |||
| pop. | 1D | 1C | 2D | 2C | 1D | 1C | 2D | 2C | 1D | 1C | 2D | 2C |
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| 1F | 1E | 2F | 2E | 1F | 1E | 2F | 2E | 1F | 1E | 2F | 2E |
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| 1H | 1G | 2H | 2G | 1H | 1G | 2H | 2G | 1H | 1G | 2H | 2G |
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CPU#3 | 0 | #2 | ||||||||||||
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CPU#4 | 0 | #2 | ||||||||||||
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CPU#5 | 0 | #3 | ||||||||||||
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CPU#6 | 0 | #3 | ||||||||||||
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CPU#7 | 0 | #4 | ||||||||||||
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Table 5: DIMM slot population order and mapping of DIMM slots to I/O Hubs and CPUs
360 | Maintenance Manual | RX900 S1 |
