Intel SRPL8 manual Processor Overview

Processor Overview

Each Pentium III Xeon processor is packaged in a single edge contact (S.E.C.) cartridge. The cartridge includes:

∙The processor core with an integrated 32 KB primary (L1) cache

∙The secondary (L2) cache

∙A thermal plate

∙A back cover

Processors used with the SRPL8 server must be:

∙5/12 volts

∙100 MHz FSB

∙1 or 2 MB cache

∙Validated by Intel for SRPL8 systems

Each processor implements the MMX™ technology with streaming SMID extensions and maintains full backward compatibility with the 8086, 80286, Intel386™ , Intel486™ , Pentium, and Pentium Pro processors. The processor’s numeric coprocessor significantly increases the speed of floating-point operations and complies with ANSI/IEEE standard 754-1985.

Each S.E.C. cartridge connects to one of two processor mezzanine boards through a 330-pin

Slot 2 edge connector (SC330.1). The cartridge is secured to the mezzanine carrier by a retention bracket. Each mezzanine board connects to the profusion carrier. Depending on configuration, your system has one to eight processors.

The processor external interface is multiprocessor (MP)-ready and operates at 100 MHz. The processor contains a local APIC unit for interrupt handling in MP and uniprocessor

(UP) environments.

The L2 cache is located on the same die as the processor core and L1 cache. The cache:

∙Is offered in 1 MB and 2 MB configurations

∙Is ECC protected

∙Operates at the full core clock rate

24 Boardset Description