Theory of Operation

Table 3-1: Run modes (Cont.)

Modes

Descriptions

 

 

G￿ted

The w￿veform is output only while:

 

￿ An extern￿l trigger sign￿l from the TRIG IN connector on the re￿r p￿nel.

 

￿ A g￿te sign￿l through the FORCE TRIGGER button ￿on the re￿r p￿nel￿ is

 

TRUE.

 

￿ A control comm￿nd such ￿s trigger or event from remote device.

 

 

Enh￿nced

The w￿veform is obt￿ined, in the order defined with the sequence, b￿sed on:

 

￿ A trigger sign￿l ￿for ex￿mple, ￿n extern￿l trigger sign￿l from the TRIG IN

 

connector on the re￿r p￿nel￿.

 

￿ An extern￿l trigger sign￿l from the TRIG IN connector on the re￿r p￿nel.

 

￿ An event sign￿l from the EVENT IN connector on the re￿r p￿nel.

 

￿ An trigger sign￿l from the FORCE TRIGGER button on the front p￿nel.

 

￿ An event sign￿l from the FORCE EVENT button on the front p￿nel.

 

￿ A control comm￿nd such ￿s trigger, event or jump from remote device.

 

 

Analog Circuit. The Analog Circuit block contains the Filter, Attenuator, Output Amplifier, Calibration and Offset Circuits. These circuits are used to process signals generated from the DAC. Option 02 has Calibration Circuits only.

Memory Address Control. The Memory Address Control controls the addresses used to read waveform memory data.

This block loads the first address of the waveform into the Address Counter that was loaded into the waveform memory. It loads the waveform data length to the Length Counter. The Address Counter specifies the point from which the waveform was generated and the Length Counter waveform ending position.

The Address and Length Counters operate with clocks produced by quarter frequency-division for the clocks from the clock oscillator.

If the repeat count value has been loaded in the Repeat Counter, the waveform is generated the specified number of times.

This block controls the sequence to the event signals generated in Enhanced Mode.

Figure 3±3 shows the relationship between the memory address control and the waveform memory.

AWG710 Service Manual

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