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Chapter 5: Constraining the Core

the following examples, the target performance is 340 Mbps. Please ensure that modifications to these constraints do not create paths that are unconstrained.

Time Names for Clocks

The following Sink core clock constraints are required:

NET “RDClk_P” TNM_NET = “RDClk_P”;

NET "<snk_instance_name>/U0/cal0/EnRSClk_int*" TNM = FFS snk_cal_flops;

The following Sink core user-interface-clock constraints are required when the example design is used, and the user interface signals are looped back to the source core interface.

NET "CalClk" TNM_NET = "CalClk";

NET "LoopbackClk" TNM_NET = "LoopbackClk";

The following Sink core user interface clock constraints are only required when the respective clocks are used.

NET "SnkCalClk" TNM_NET = "SnkCalClk";

NET "SnkFFClk" TNM_NET = "SnkFFClk";

NET "SnkStatClk" TNM_NET = "SnkStatClk";

Timespecs for Clocks

These constraints specify the frequency and duty cycle of the clock signal. For high frequency clocks, clock jitter is also specified. These values can be modified according to user design.

The following Sink core clock constraints are always required. The generated SPI-4.2 Lite core may have different timing constraints than the examples provided.

TIMESPEC "TS_RDClk_P" = PERIOD "RDClk_P" 170MHz HIGH 50% INPUT_JITTER 300ps;

TIMESPEC "TS_SnkCalFlops" = FROM "snk_cal_flops" TO "snk_cal_flops" "TS_RDClk_P"/ 4;

The following Sink core user interface clock constraints are required when the example design is used, and the user interface signals are looped back to the source core interface.

TIMESPEC "TS_CalClk" = PERIOD "CalClk" 43MHz HIGH 50%;

TIMESPEC "TS_LoopbackClk" = PERIOD "LoopbackClk" 170MHz HIGH 50% INPUT_JITTER 300ps;

The following Sink core user interface clocks constraints are only required when the respective clocks are used.

TIMESPEC "TS_SnkCalClk" = PERIOD "SnkCalClk" 43MHz HIGH 50%;

TIMESPEC "TS_SnkFFClk" = PERIOD "SnkFFClk" 170MHz HIGH 50% INPUT_JITTER 111ps;

TIMESPEC "TS_SnkStatClk" = PERIOD "SnkStatClk" 43MHz HIGH 50%;

Maxdelay for Reset

The following Sink core reset signal constraints are always required. Once generated, the SPI-4.2 Lite core may have different timing constraints than the examples provided below.

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

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Xilinx UG181 manual Time Names for Clocks, Timespecs for Clocks, Maxdelay for Reset, Constraining the Core

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.