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Xilinx UG181 Designing with the Core, General Design Guidelines, Know the Degree of Difficulty

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Chapter 4

Designing with the Core

This chapter contains general design guidelines, detailed descriptions about the behavior of each interface, example waveforms, and implementation considerations. To design an application using the SPI-4.2 Lite core, follow the guidelines provided in this chapter.

General Design Guidelines

This section describes the steps required to implement each feature of the SPI-4.2 Lite core into a fully-functioning design integrated with user application logic. Remember that not all designs will require all steps listed in this chapter.

We recommend you to follow the guidelines below for optimum results.

Know the Degree of Difficulty

A fully compliant SPI-4.2 Lite core is challenging to implement in any technology.

The degree of difficulty is significantly influenced by the following:

•Maximum system clock frequency

•Targeted device architecture

•Specific user application

All implementations require careful attention to system performance requirements. Pipelining, placement constraints, and logic duplication are all methods you can use to improve system performance.

Understand Signal Pipelining

Due to the nature of packet protocols, it is important to understand that the SPI-4.2 Lite Sink and Source cores have been pipelined to maximize performance. The 32- or 64-bit data written into the Source core user interface takes several clock cycles before appearing on the SPI-4.2 interface. This is due to the pipelining required to format the packet, create control words, calculate DIP4, etc.

Similarly, SPI-4.2 packets that are received by the Sink core take several clock cycles before appearing on the user interface. This is due to the pipelining required to convert the streaming input bus to an aligned output with packet information, error signals, and so on. The exact latency of the Sink and Source cores will vary based upon core configuration, and is best determined through simulation.

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual Designing with the Core, General Design Guidelines, Know the Degree of Difficulty

Contents

UG181 June 27 LogiCORE IP SPI-4.2 LiteDate Version Revision SPI-4.2 Lite v4.3 User Guide UG181 June 27Table of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide 1SPI-4.2 Lite Core in a Typical Link Layer Application Schedule of Figures30Addressable Status Fifo Interface 4-Channel Configuration Generating the Core Designing with the Core Schedule of TablesAppendix a SPI-4.2 Lite Control Word About This Guide ContentsTypographical ConventionsConventions Online DocumentPreface About This Guide Additional Core Resources IntroductionAbout the Core Recommended Design ExperienceDocument Technical SupportFeedback SPI-4.2 Lite CoreSystem Overview Core ArchitectureSink Core Source CoreCore Architecture Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram RCtlN Sink SPI-4.2 InterfaceSink Control and Status Interface Sink User InterfaceSink Fifo Interface 3Sink Fifo Signals NameCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate RDClk0 General Purpose Sink Clocking InterfaceRDClk0USER This clock Source Core InterfacesSource Core Interfaces Source SPI-4.2 InterfaceDomain Source User InterfaceSource Control and Status Interface 16 bytes with no EOP Name Direction Clock Description Domain Source Fifo Interface14 Source Status Fifo Signals Source Status Address Source Static Configuration InterfaceSource Almost Full Threshold Assert Source Calendar Period The SrcCalendarM Source Clocking InterfaceSysClk0 General Purpose Domain Core Architecture Core Generator Graphical User Interface Generating the CoreCore Options Main ScreenSink Status Options Screen Component NameCalendar Flow ControlStatus Interface Sink Other Options Screen SynchronizationFifo Threshold Clock Distribution Clock ModeSource Status Options Screen ClockingBursting Source Other Options ScreenTSClk Distribution Burst ModeBurst Size in Credits SysClk DistributionCalendar COE File Format Know the Degree of Difficulty Understand Signal PipeliningDesigning with the Core General Design GuidelinesUse Supported Design Flows Recognize Timing Critical SignalsInitializing the SPI-4.2 Lite Core Keep it RegisteredSink Data Path Example Sink CoreBasic Operation SPI-4.2 Interface1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP Sink Fifo RCtlSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Almost Empty Sink Fifo Interface SignalsSink Almost Full Sink Fifo EmptySink Overflow Sink Status and Flow Control SignalsInitializing the Calendar In-Circuit Sink Calendar Initialization7Sink Calendar Initialization Sink Flow Control8Typical Flow Control Implementation for 4-Channel System 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3 Sink Status Fifo Interface ExampleSink Status Fifo Status Interface Example FifoAFMode and Sink Almost Full Sink Static Configuration SignalsInsertion of DIP2 Errors Fifo Almost Full Mode12FIFO Almost Full Mode DCM Alignment Implementation Considerations Fifo Almost Full Mode 10 orSink Data Capture Implementation Static AlignmentSynchronization and Start-up Reset HuntSync Wait In-Frame and Out-of-Frame Behavior Error HandlingSync Data Sync TrainLoss of RDClk Sink Fifo Burst ErrorSink SPI-4.2 Bus Error and Sink Bus Error Status70 EOP Abort HandlingSink DIP-4 Error Handling Sequential Payload Control WordsSequential End-of-Burst Control Words 18Example of Error Flag SnkFFDIP4Err Reserved Control Words Source CoreSource Core Source Data Path Example22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Inserting DIP4 Errors Source Control and Status SignalsTransmitting Idle Cycles Source Fifo Almost Full Source Fifo Interface Signals24Source Fifo Almost-full Condition Source Fifo OverflowSource Status and Flow Control Signals Insertion of DIP-4 ErrorsWriting to the Source Fifo 27Typical User Design Example Source Calendar Initialization28Source Calendar Initialization Source Flow Control Addressable Status Interface29Addressable Status Fifo Interface Addressable Status Fifo Interface Example30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Burst Mode Source Static Configuration Signals35Example Of Source Burst Mode = Source Burst Mode ExampleReset Source Out of Frame Source Behavior Before SynchronizationSource Behavior After Synchronization EOP Abort InsertionIncorrect Burst Termination Source DIP-2 Error HandlingSource Pattern Error Handling Source Status Frame Word HandlingDesigning with the Core Timing Constraints Constraining the CoreOverview Sink Core Required ConstraintsConstraining the Core Maxdelay for ResetTime Names for Clocks Timespecs for ClocksSink Core Required Constraints Phase Shift for DCMClock Delay in Iserdes DCM and Static Alignment ConstraintsPlacement Placement ConstraintsIOB Register Packing IDelayCtrlSink Core Optional Constraints Standards ConstraintsTimenames for Clocks Source Core Required ConstraintsArea Group Constraints Timing Ignore ConstraintsSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsUser Constraints Constraints MigrationNew Target Region or Device Package Source Core Modifying the UCF FileTarget Device Sink CoreInst TSClk LOC = Bank3 Special Design Considerations Sink Clocking OptionsEmbedded Clocking Special Design Considerations User ClockingGlobal Clocking Sink Clocking Options2Sink Core User Clocking Resources Clocking Option 3Sink User Clocking Global Clocking Regional ClockingSource Clocking Options Source Clocking Options5Source Clocking Master and Slave Implementation Master ClockingIOB 8Source Clocking Regional Clocking for SysClk Slave Clocking 3SysClk Clocking Resources Clocking OptionTSClk Clocking Resources Clocking Option Instantiating Multiple Cores Multiple Core ImplementationsGenerating the Cores Creating Top-Level UCF FileMultiple Core Implementations Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Generating a Simulation Model with Initialized Calendar Simulating and Implementing the CoreFunctional Simulation Generating a Simulation ModelSimulating and Implementing the Core Timing SimulationSynthesis SynthesisSynthesis of Example Design SynplifyMapping the Design Xilinx Tool FlowExample Design Script NGDBuildStatic Timing Analysis Generating a BitstreamXilinx Tool Flow 130 Eops SPI-4.2 Lite Control WordDIP-4 Example SPI-4.2 Lite Calendar ProgrammingAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification