Xilinx UG181 manual Sink Clocking Interface, RDClk0 General Purpose

Sink Core Interfaces

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Sink Clocking Interface

The Sink core supports two clocking implementations: embedded clocking and user clocking. The embedded clocking configuration provides a complete solution with the clock circuitry embedded within the Sink core. The user clocking configuration allows the clocking scheme to be implemented external to the Sink core.

A list of the Sink clocks for embedded clocking and their description is provided in Table 2-7. Table 2-8defines the DCM reset and clock status signals, and Table 2-9defines the user clocking signals. The minimum frequency for all clocks is dependent on the minimum frequency of the DCM.

Table 2-7:Sink Core Clocks: Embedded Clocking

Clock Pins	Direction	Description	Max. Frequency
RDClk0_GP	Output	RDClk0 General Purpose:	Virtex-5: 275 MHz
	(User Interface)	This clock is the full Rate	Virtex-4: 190 MHz
		Receive Data Clock. It is
			Virtex-II Pro: 160 MHz
		used for clocking the
			Virtex-II: 160 MHz
		internal logic of the core and
		is routed to the User	Spartan-3: 115 MHz
		Interface for use by the	Spartan-3E: 90 MHz
		user’s logic.
			Spartan-3A/3AN/3A DSP:
			105 MHz
RDClk180_GP	Output	RDClk180 General	Virtex-5: 275 MHz
	(User Interface)	Purpose: This clock is the	Virtex-4: 190 MHz
		inverted equivalent of
			Virtex-II Pro: 160 MHz
		RDClk0_GP. It is used for
			Virtex-II: 160 MHz
		clocking the internal logic of
		the core and is routed to the	Spartan-3: 115 MHz
		User Interface for use by the	Spartan-3E: 90 MHz
		user’s logic.
			Spartan-3A/3AN/3A DSP:
			105 MHz

Table 2-8:Sink Core Clocks: Status Signals

Name	Direction	Clock	Description
		Domain
DCMReset_RDClk	Input	N/A	Reset of RDClk’s DCM
Locked_RDClk	Output	N/A	Locked status of RDClk’s DCM
DCMLost_RDClk	Output	N/A	Indicates RDClk input has stopped (status bit
			one of RDClk DCM)
SnkClksRdy	Output	N/A	Indicates all Sink core clocks are ready for use

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UG181 June 27, 2008