Sink Core Interfaces

R

Sink Clocking Interface

The Sink core supports two clocking implementations: embedded clocking and user clocking. The embedded clocking configuration provides a complete solution with the clock circuitry embedded within the Sink core. The user clocking configuration allows the clocking scheme to be implemented external to the Sink core.

A list of the Sink clocks for embedded clocking and their description is provided in Table 2-7. Table 2-8defines the DCM reset and clock status signals, and Table 2-9defines the user clocking signals. The minimum frequency for all clocks is dependent on the minimum frequency of the DCM.

Table 2-7:Sink Core Clocks: Embedded Clocking

Clock Pins

Direction

Description

Max. Frequency

 

 

 

 

RDClk0_GP

Output

RDClk0 General Purpose:

Virtex-5: 275 MHz

 

(User Interface)

This clock is the full Rate

Virtex-4: 190 MHz

 

 

Receive Data Clock. It is

 

 

Virtex-II Pro: 160 MHz

 

 

used for clocking the

 

 

Virtex-II: 160 MHz

 

 

internal logic of the core and

 

 

is routed to the User

Spartan-3: 115 MHz

 

 

Interface for use by the

Spartan-3E: 90 MHz

 

 

user’s logic.

 

 

Spartan-3A/3AN/3A DSP:

 

 

 

 

 

 

105 MHz

 

 

 

 

RDClk180_GP

Output

RDClk180 General

Virtex-5: 275 MHz

 

(User Interface)

Purpose: This clock is the

Virtex-4: 190 MHz

 

 

inverted equivalent of

 

 

Virtex-II Pro: 160 MHz

 

 

RDClk0_GP. It is used for

 

 

Virtex-II: 160 MHz

 

 

clocking the internal logic of

 

 

the core and is routed to the

Spartan-3: 115 MHz

 

 

User Interface for use by the

Spartan-3E: 90 MHz

 

 

user’s logic.

 

 

Spartan-3A/3AN/3A DSP:

 

 

 

 

 

 

105 MHz

 

 

 

 

Table 2-8:Sink Core Clocks: Status Signals

Name

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

DCMReset_RDClk

Input

N/A

Reset of RDClk’s DCM

 

 

 

 

Locked_RDClk

Output

N/A

Locked status of RDClk’s DCM

 

 

 

 

DCMLost_RDClk

Output

N/A

Indicates RDClk input has stopped (status bit

 

 

 

one of RDClk DCM)

 

 

 

 

SnkClksRdy

Output

N/A

Indicates all Sink core clocks are ready for use

 

 

 

 

SPI-4.2 Lite v4.3 User Guide

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UG181 June 27, 2008

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Xilinx UG181 manual Sink Clocking Interface, RDClk0 General Purpose
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UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

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In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.
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