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Xilinx UG181 manual Source Calendar Initialization, 27Typical User Design Example

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Chapter 4: Designing with the Core

Source Core

FIFO

Status I/F

User

Interface

MUX

POLLING

Arbiter

FIFO

Channel 0

FIFO

Channel 1

Figure 4-27:Typical User Design Example

To enable designing back-end user logic, the Source core presents status information in two ways:

•Addressable Status Interface. This interface allows polling the status of 16 channels at a time. This polling is synchronous to a user-defined clock (SrcStatClk). Additionally, the last channel receiving a status update on TStat[1:0] is presented (synchronous to TSClk).

•Transparent Status Interface. This interface presents status information as it is received on TStat[1:0] with minimal latency. It also provides the ideal interface to customize how to process the FIFO status information as it is received.

A user-programmable calendar is also provided. This calendar stores the order and frequency that each channel status that is received on TStat, which is identical to the sequence defined by the device that is receiving data from the Source interface. This is the mechanism that enables the interfaces to determine which channel status is being received on TStat. As defined by the SPI-4.2 specification, there are two bits provided for each channel, indicating the channel status (hungry=01, starving=00, satisfied=10).

These interfaces are described in greater detail in the following sections. Descriptions of the Source Status Path signals are provided in Table 2-13and Table 2-14, page 36.

Source Calendar Initialization

There are two ways to initialize the Source calendar. The calendar can be initialized by loading the COE file in the CORE Generator GUI. This loads the calendar contents into the UCF file. For more information, see Chapter 3, “Generating the Core.” If this method is not used, the calendar must be initialized in-circuit at startup.

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UG181 June 27, 2008

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Xilinx UG181 manual Source Calendar Initialization, 27Typical User Design Example
Page 85 Page 87

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.