R

Chapter 4: Designing with the Core

Status for 16 channels each clock cycle can be written. The SnkStatAddr bus is used to select which 16 channels are written, and the core supports configurations of 1–256 channels. The 16 channels of FIFO Status that are written are addressed as follows:

Bank 0: SnkStatAddr[3:0]=0 for channels 15 to 0

Bank 1: SnkStatAddr[3:0]=1 for channels 31 to 16

Bank 2: SnkStatAddr[3:0]=2 for channels 47 to 32

Bank 3: SnkStatAddr[3:0]=3 for channels 63 to 48

...

Bank 14: SnkStatAddr[3:0]=14 for channels 239 to 224

Bank 15: SnkStatAddr[3:0]=15 for channels 255 to 240

The status that is written is mapped to the 16-bit bus as follows:

For Bank 0: SnkStatAddr[3:0]=0

SnkStat[1:0] => Channel 0, where SnkStat[1] is the MSB of the 2-bit status

SnkStat[3:2] => Channel 1

SnkStat[5:4] => Channel 2

...

SnkStat[11:10] => Channel 13

SnkStat[13:12] => Channel 14

SnkStat[15:14] => Channel 15

SPI-4.2 Sink Core

FIFO

Status I/F

User

Interface

MUX

Flow Control

Status:

Starving

Hungry

Satisfied

FIFO

Channel 0

FIFO

Channel 1

FIFO

Channel 2

FIFO

Channel 3

Programmable

Full

Figure 4-8:Typical Flow Control Implementation for 4-Channel System

64

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

Page 64
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Xilinx UG181 manual 8Typical Flow Control Implementation for 4-Channel System

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.