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Xilinx UG181 manual User Clocking, Special Design Considerations

Models: UG181

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Chapter 6: Special Design Considerations

BUFG

RDClk0_USER

100MHz

RDClk180_USER

CLK0 DCM

CLK180

CLK2X

IBUFGDS

RDClk

100 MHz

IOB

DCMReset_RDClk

Locked_RDClk

Denotes I/O on User Interface

100 MHz Path

IOB DDR Flops

Sink Internal

Data & Control

Bus

16

32

Q D

RDClk0_GP16

100 MHz

200 MHz Path

QD

Q D

RDat[15:0] & RCtl

RDClk0_GP

100 MHz

RDClk180_GP 100 MHz

IOB

	Internal Bus					RStat[1:0] & RSClk
	Internal Bus		D		Q	RStat[1:0] & RSClk	IOB
RStat[1:0] & RSClk			D		Q	25 MHz	IOB
RStat[1:0] & RSClk						25 MHz
	RDClk0_GP
		100 MHz		EN
	Enable at ¼ (or 1/8) PL4 Rx data rate

Figure 6-1:Embedded Clocking Option

User Clocking

The Sink user clocking configuration allows users to fully customize the way the Sink core clocks are implemented. An example file is provided (pl4_lite_snk_clk.v/.vhd) that shows how to implement a clocking module for the Sink core. An illustration of the User clock inputs and this example module are shown in Figure 6-2and the user inputs are

112	www.xilinx.com	SPI-4.2 Lite v4.3 User Guide
		UG181 June 27, 2008

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Xilinx UG181 manual User Clocking, Special Design Considerations

Contents

LogiCORE IP SPI-4.2 Lite UG181 June 27SPI-4.2 Lite v4.3 User Guide UG181 June 27 Date Version RevisionTable of Contents Designing with the Core Appendix C SPI-4.2 Lite Core Verification SPI-4.2 Lite v4.3 User Guide Schedule of Figures 1SPI-4.2 Lite Core in a Typical Link Layer Application30Addressable Status Fifo Interface 4-Channel Configuration Schedule of Tables Generating the Core Designing with the CoreAppendix a SPI-4.2 Lite Control Word Contents About This GuideConventions TypographicalOnline Document ConventionsPreface About This Guide Introduction About the CoreRecommended Design Experience Additional Core ResourcesTechnical Support FeedbackSPI-4.2 Lite Core DocumentCore Architecture System OverviewSource Core Sink CoreCore Architecture Sink Core Interfaces Sink Core InterfacesSink Core Block Diagram Sink SPI-4.2 Interface RCtlNSink User Interface Sink Control and Status Interface3Sink Fifo Signals Name Sink Fifo InterfaceCore Architecture 3Sink Fifo Signals Name Sink Core Interfaces Sink Static Configuration Interface Number of Complete Training Sequences a Sink Almost Full Threshold Negate Sink Clocking Interface RDClk0 General PurposeSource Core Interfaces RDClk0USER This clockSource SPI-4.2 Interface Source Core InterfacesSource User Interface DomainSource Control and Status Interface 16 bytes with no EOP Source Fifo Interface Name Direction Clock Description Domain14 Source Status Fifo Signals Source Static Configuration Interface Source Status AddressSource Almost Full Threshold Assert Source Clocking Interface Source Calendar Period The SrcCalendarMSysClk0 General Purpose Domain Core Architecture Generating the Core Core Generator Graphical User InterfaceMain Screen Sink Status Options ScreenComponent Name Core OptionsFlow Control CalendarStatus Interface Synchronization Sink Other Options ScreenFifo Threshold Clock Mode Source Status Options ScreenClocking Clock DistributionSource Other Options Screen BurstingBurst Mode Burst Size in CreditsSysClk Distribution TSClk DistributionCalendar COE File Format Understand Signal Pipelining Designing with the CoreGeneral Design Guidelines Know the Degree of DifficultyRecognize Timing Critical Signals Initializing the SPI-4.2 Lite CoreKeep it Registered Use Supported Design FlowsSink Core Basic OperationSPI-4.2 Interface Sink Data Path Example1SPI-4.2 Interface to the 64-Bit User Interface SnkFFSOP SnkFFEOP RCtl Sink FifoSPI-4.2 Control Word Mapping to 32-bit User Interface Sink Control and Status Signals Sink Fifo Interface Signals Sink Fifo Almost EmptySink Fifo Empty Sink Almost FullSink Status and Flow Control Signals Sink OverflowSink Calendar Initialization Initializing the Calendar In-CircuitSink Flow Control 7Sink Calendar Initialization8Typical Flow Control Implementation for 4-Channel System Sink Status Fifo Interface Example 2,3 None CH 1,2 CH 0,3 CH 0,1,2,3Sink Status Fifo Status Interface Example Sink Static Configuration Signals Insertion of DIP2 ErrorsFifo Almost Full Mode FifoAFMode and Sink Almost Full12FIFO Almost Full Mode Fifo Almost Full Mode 10 or Sink Data Capture ImplementationStatic Alignment DCM Alignment Implementation ConsiderationsSynchronization and Start-up Hunt ResetSync Wait Error Handling Sync DataSync Train In-Frame and Out-of-Frame BehaviorSink Fifo Burst Error Sink SPI-4.2 Bus Error and Sink Bus Error Status70EOP Abort Handling Loss of RDClkSequential Payload Control Words Sink DIP-4 Error HandlingSequential End-of-Burst Control Words 18Example of Error Flag SnkFFDIP4Err Source Core Reserved Control WordsSource Data Path Example Source Core22Source Data Path Minimum SOP Spacing Enforced SrcFFData630 TDat SPI-4.2 Lite v4.3 User Guide Transmitting Training Patterns Source Control and Status Signals Inserting DIP4 ErrorsTransmitting Idle Cycles Source Fifo Interface Signals Source Fifo Almost FullSource Fifo Overflow 24Source Fifo Almost-full ConditionInsertion of DIP-4 Errors Source Status and Flow Control SignalsWriting to the Source Fifo Source Calendar Initialization 27Typical User Design ExampleSource Flow Control Addressable Status Interface 28Source Calendar InitializationAddressable Status Fifo Interface Example 29Addressable Status Fifo Interface30Addressable Status Fifo Interface 4-Channel Configuration Bank None Source Flow Control Transparent Status Interface 33Transparent Status Fifo Interface Block Diagram Source Static Configuration Signals Source Burst ModeSource Burst Mode Example 35Example Of Source Burst Mode =Reset Source Behavior Before Synchronization Source Behavior After SynchronizationEOP Abort Insertion Source Out of FrameSource DIP-2 Error Handling Source Pattern Error HandlingSource Status Frame Word Handling Incorrect Burst TerminationDesigning with the Core Constraining the Core OverviewSink Core Required Constraints Timing ConstraintsMaxdelay for Reset Time Names for ClocksTimespecs for Clocks Constraining the CorePhase Shift for DCM Clock Delay in IserdesDCM and Static Alignment Constraints Sink Core Required ConstraintsPlacement Constraints PlacementIDelayCtrl Sink Core Optional ConstraintsStandards Constraints IOB Register PackingSource Core Required Constraints Area Group ConstraintsTiming Ignore Constraints Timenames for ClocksSource Core Required Constraints Inst SysClk LOC = Bank9 Source Core Optional Constraints Source Core Optional ConstraintsConstraints Migration User ConstraintsNew Target Region or Device Package Modifying the UCF File Target DeviceSink Core Source CoreInst TSClk LOC = Bank3 Sink Clocking Options Special Design ConsiderationsEmbedded Clocking User Clocking Special Design ConsiderationsSink Clocking Options Global Clocking2Sink Core User Clocking Resources Clocking Option Regional Clocking 3Sink User Clocking Global ClockingSource Clocking Options Source Clocking OptionsMaster Clocking 5Source Clocking Master and Slave ImplementationIOB 8Source Clocking Regional Clocking for SysClk 3SysClk Clocking Resources Clocking Option Slave ClockingTSClk Clocking Resources Clocking Option Multiple Core Implementations Instantiating Multiple CoresCreating Top-Level UCF File Generating the CoresMultiple Core Implementations Clocking Considerations SPI-4.2 Lite v4.3 User Guide 123 124 Simulating and Implementing the Core Functional SimulationGenerating a Simulation Model Generating a Simulation Model with Initialized CalendarTiming Simulation Simulating and Implementing the CoreSynthesis Synthesis of Example DesignSynplify SynthesisXilinx Tool Flow Example Design ScriptNGDBuild Mapping the DesignGenerating a Bitstream Static Timing AnalysisXilinx Tool Flow 130 SPI-4.2 Lite Control Word EopsDIP-4 SPI-4.2 Lite Calendar Programming ExampleAppendix B SPI-4.2 Lite Calendar Programming SPI-4.2 Lite Core Verification Appendix C SPI-4.2 Lite Core Verification