R

Chapter 4: Designing with the Core

Reserved Control Words

As defined by the OIF SPI-4.2specification, a reserved control word contains an SOP, but the payload control bit (RDat[15]) is not set to a one. If this occurs and is followed by data, the Sink core asserts SnkFPayloadErr for the duration of the burst, indicating that the burst did not have a correct payload control word. This indicates that the SOP and address configuration will not be valid. This error will also be flagged on SnkBusErr. This behavior is illustrated in Figure 4-20.

If this behavior occurs and is not followed by data, then the Sink core drops the control word and asserts the output SnkBusErr.

SPI-4.2 Interface

IDLE

SOP

DATA

DATA

DATA

EOP

IDLE

Reserved Ctl word detected:

RDat[15]=0

RDat[12]=1

User Interface

Addr=prev Addr

Addr

Addr

SOP=0

--

EOP

Data

Data

Data

SnkFFPayloadErr

SnkFFPayloadErr

SnkFFPayloadErr

Figure 4-20:Example of Error Flag SnkFFPayloadErr

Source Core

Basic Operation

The Source core receives 32-bit or 64-bit data on the user interface and converts data to 16- bit data which is transferred across the SPI-4.2 interface. It also receives flow control information of the SPI-4.2 interface and processes it into 32-bit or 2-bit status word, depending on the status FIFO interface— accessible through the user interface.

The following sections explain how the Source core operates. See “Source Core Interfaces,” page 30 for the signal list of the interfaces.

Source SPI-4.2 Interface

The SPI-4.2 user interface combines data words and out-of-band control signals and multiplexes them to the SPI-4.2 16-bit databus. This allows the user interface to run at half (64-bit interface) or a quarter (32-bit interface) of the data rate. For example, for a 200 Mbps SPI-4.2 data rate and a 32-bit user interface, you can write data into the Source core at

100 MHz. With a 64-bit user interface, one can write data into the Source core at 50 MHz and maintain the same data rate.

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SPI-4.2 Lite v4.3 User Guide

 

 

UG181 June 27, 2008

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Xilinx UG181 manual Source Core, Reserved Control Words

UG181 specifications

Xilinx UG181 refers to the User Guide for the Xilinx 7 Series FPGAs, which offers a comprehensive overview of the architecture, capabilities, and features of these powerful field-programmable gate arrays (FPGAs). Designed to cater to a wide range of applications, Xilinx 7 Series FPGAs are widely adopted in industries such as telecommunications, automotive, aerospace, and consumer electronics.

One of the main features of the Xilinx 7 Series FPGAs is their use of advanced 28nm technology, which enables them to achieve high performance while maintaining low power consumption. This fine process technology not only ensures better power efficiency but also allows for increased logic density. The 7 Series includes several families, such as Artix-7, Kintex-7, and Virtex-7, each tailored for specific application demands ranging from cost-sensitive solutions to high-performance data processing.

Xilinx 7 Series FPGAs also incorporate a rich set of programmable logic resources. This includes Look-Up Tables (LUTs), Flip-Flops, and Digital Signal Processing (DSP) slices that have been optimized for various arithmetic functions. With several thousands of logic cells available, designers can implement complex algorithms and systems directly in hardware for improved performance over traditional software solutions.

In addition to their logic capabilities, Xilinx 7 Series FPGAs feature an array of high-speed serial communication interfaces. These include support for technologies like PCI Express, Gigabit Ethernet, and Serial RapidIO, which facilitate efficient data transfer and integration into enterprise-level systems. The presence of high-speed transceivers also makes them ideal for applications that require fast data handling like video processing or high-frequency trading.

Furthermore, these FPGAs offer extensive memory options, including support for a wide range of external memory interfaces. This versatility allows for the integration of high-bandwidth memory solutions, which is essential for performance-intensive applications. With the introduction of the Memory Controller IP, users can easily connect various memory types, ensuring flexibility in system design.

Finally, Xilinx has made significant strides in development tools for 7 Series FPGAs, providing a robust ecosystem for design engineers. With design suites such as Vivado and SDK, users benefit from a comprehensive platform for deciding, simulating, and implementing designs efficiently. The combination of advanced hardware capabilities and powerful software tools solidifies the position of Xilinx 7 Series FPGAs as a preferred choice for custom digital hardware design across various industries.